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Usually, when designing a convolutional encoder for a transmitter, some sort of termination mechanism is applied to drive the encoder back to its zero-state after a message was transmitted. This is often done by appending a tail sequence to the transmitted message, e.g. a certain number (n) of zeros in case of a convolutional encoder without feedback. This way it takes n clock cylces to return the encoder to the all zero sate.
On the other hand, e.g. when implementing a convolutional encoder in HDL, this reset to the zero state could also be achieved by simply resetting all (shift)registers of the encoder. That way the zero state could be reached after only one clock cycle.
In the literature I never saw anyone mention the second method and was wondering what is the reason for terminating a convolutional encoder with a tail sequence instead of simply resetting the state registers?

EDIT: If the convolutional encoder contains feedback, additional circuitry is required to calculate an adequate termination tail to drive the encoder back to zero(a system of linear equations must be solved). So why would anyone trade the 'simple' reset solution for a solution consuming more hardware and time?
(My specific case concerns LDPC convolutional codes, which can have deep encoder memory, so the time required for terminating the code is not negligible.)

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A convolutional encoder is a finite state machine whose output continues for several clock cycles after the input has ended (and of course depends on the input). What is called a feedforward encoder typically has a FIFO buffer through which the input data bits progress and ultimately fall off the end. This part of the encoder output has valuable information (parity checks on the data bits still in the buffer) that the decoder uses in correcting errors at the receiver end. Thus, resetting the encoder to zero state right after the last data bit has entered the buffer is not a good idea. It is better to pump in zeros until the last data bit has fallen off the end of the buffer (and to transmit the corresponding encoder output bits to the decoder for use in the decoding process). For a feedback encoder, there can be issues with poorly designed encoders in that the buffer may never empty out, but such encoders are rare in practice.

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  • \$\begingroup\$ Thanks for your reply. So as I understand appending a termination tail to the information sequence basically ensures that all transmitted data bits are protected equally well against errors, because this way each information bit will occur in the same number of parity check equations. If the encoder is just reset after the last data bit enters it, the last few data bits will not be protected as well as the rest of the data bits. But then it should be possible for an encoder with memory depth m to append m zeros to the data sequence and THEN reset the encoder regardless of feedback...? \$\endgroup\$
    – andrsmllr
    Commented Jan 8, 2013 at 22:15
  • \$\begingroup\$ @damage Your first statement is correct. For a feedforward encoder with memory depth \$m\$, the buffer is emptied of all data bits when the last of the tail \$m\$ zeroes enters the buffer. With feedback encoders, and with LDPC codes, turbo codes, etc. look for things like _tail-biting codes also which might have special requirements for how many zeroes need to be pumped in (and the corresponding bits transmitted) to get good performance. Most Viterbi decoders for conventional convolutional codes manage with the standard tail length. \$\endgroup\$
    – Dilip Sarwate
    Commented Jan 8, 2013 at 22:31
  • \$\begingroup\$ Thanks again. I read through several papers on tail-biting codes already, but they are not really what I am looking for because continuous en-/decoding is not possible - they are in fact block codes encoded by convolutional encoders(+ wrap around). My question was originally motivated by the fact that I have to decide how to terminate my codes, either by a term. sequence(calculated from the current encoder state and the parity matrix) to drive the encoder back to zero, or by just pumping zeros in (to ensure all bits are equally well protected) and then resetting the encoder directly. \$\endgroup\$
    – andrsmllr
    Commented Jan 8, 2013 at 23:07
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There's fundamentally no reason why a single reset state could NOT be asserted in ANY logic design, not just in a HDL. So the answer must be fundamental to the application or the coding scheme and how that affects the it's spectral characteristics. You'd have to be more specific in your use for someone to be able to tell if zero padding is desired or even needed.

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  • \$\begingroup\$ What I am describing above is not 'really' zero padding in the classical way the word is used. Encoding takes place before any modulation is applied and spectral characteristics are not really of importance (yet). The zeros appended in this case are only a termination sequence to return the encoder to a known and well defined state. (My reference to HDL was also just an example. Anyway I'll edit my question a little.) \$\endgroup\$
    – andrsmllr
    Commented Jan 8, 2013 at 18:47
  • \$\begingroup\$ BTW I agree with you, that there is no reason why this could not in general be done. The question is: WHY isn't it done? \$\endgroup\$
    – andrsmllr
    Commented Jan 8, 2013 at 19:00

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