As far as I know, the circuit into the read circle works as a switch. I would like you to help me to understand how does the circuit works as a switch and why I need something so complicated instead of a simple circuit with one BJT only. Also, why do I need PNP BJTs while the most of the world uses NPN BJTs?
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2\$\begingroup\$ Where did the circuit come from - please link to the source. This cannot be answered without that link. \$\endgroup\$– Andy akaCommented Nov 25, 2020 at 15:12
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\$\begingroup\$ I honestly don't know where can I get it \$\endgroup\$– Stefano FedeleCommented Nov 25, 2020 at 17:58
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1\$\begingroup\$ @StefanoFedele what nonsense is this? You post something yet claim not to know here it came from??? \$\endgroup\$– Chris StrattonCommented Nov 25, 2020 at 19:34
2 Answers
Assuming that the part number and package of the component U1 are correct, the pin 14 is the supply voltage pin of the PIC. The bipolar-based circuit is essentially connecting or disconnecting the PIC to the VCC.
Now to the circuit itself, it works as follows:
If the switch \$SW_1\$ is open
- The bipolar \$Q_1\$ is off because its emitter and base voltages are the same (diode is not forward biased)
- Since \$R_2\$ and \$R_3\$ are pulling the base of \$Q_2\$ to ground, \$Q_2\$ will be fully on, and will consequently bias the PIC (I could not figure out the reason for the resistor \$R_4\$
Now if the switch \$SW_1\$ is closed
- The emitter-base diode of the transistor \$Q_1\$ will turn on and consequently it will pull the node between \$R_2\$ and \$R_3\$ to appoximately VCC, thus turning off the transistor \$Q_2\$
- Now the PIC is off
Note: The use of PNP and NPN bipolars depends on the application. Generally PNPs are used as high side switches. The switch acts as a source (current flows out of the switch and into the load). NPNs are generally used as low side switch. The switch acts a sink for the load (current flows from the load and into the switch).
UPDATE#1 As for the further clarifications:
Jumper \$J_5\$
The output pin \$RTS\$ of the FTDI chip has a logic level high (4.1V) when its input buffer is full, and a low logic level (0.4V) when it can still accept data. I reckon the reason behind placing a jumper there, is to add a software based reset driven by the FTDI chip. The way the circuit is wired right now, it would work as follows if the jumper would be connected and \$SW1\$ is open.
\$RTS\$ is low
- FTDI is going to pull the base of \$Q_1\$ low, thus turning it on and consequently turning \$Q_2\$ off, and resetting the PIC.
\$RTS\$ is high
- Nothing much really changes since the FTDI would still try to pull up the base voltage of \$Q_1\$ to, thus turning it off. In this scenario the PIC is running and probably
The reason why the designer opted for a jumper instead of directly connecting the \$RTS\$ pin might be that, in case the \$RTS\$ pin was high (4.1V) and the switch \$SW_1\$ is pressed at the same time, you would short circuit the output pin to ground. Since this pin can source maximum 2mA, it could probably damage it.
Capacitor \$C_3\$
It simply connects the supply pin of the PIC to ground and acts as a bypass capacitor, handling high current transients.
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\$\begingroup\$ This is pretty clearly not designed to save power as it default to "on" and will itself consume power when "off". Rather it appears to be a commanded-reset circuit, which for some reason accomplishes reset by cycling power rather than driving the reset pin. Perhaps in utilized configuration the MCU doesn't have a reset input. \$\endgroup\$ Commented Nov 25, 2020 at 16:06
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\$\begingroup\$ Here is a lot of glitches in that drawing. For instance FL232 has 28 pin and pin 6 is not Vcc. What part of circuit looks like level converter, but can not be sure about-face intention of designer. By the way, PICs MCs has power saving mode. \$\endgroup\$ Commented Nov 25, 2020 at 16:22
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\$\begingroup\$ @ChrisStratton this device has a dedicated reset pin (\$\bar{MCLR}\$). \$\endgroup\$ Commented Nov 25, 2020 at 16:42
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\$\begingroup\$ As the label on SW1 makes crystal clear, this circuit exists to provide a power-interruption reset. Why that and not the MCLR is being used is a mystery unanswerable without the reset of the MCU circuit or reading the designers mind. (I can think of a chip by another maker where the reset input can be re-purposed as a GPIO, and one by yet another where a security unlock erase requires a power cycle, but even a connected I/O will leak enough current to prevent merely interrupting power from counting as that). Anyway this is most definitely not a power saving circuit. \$\endgroup\$ Commented Nov 25, 2020 at 16:59
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\$\begingroup\$ @ChrisStratton Your way of thinking makes more sense, and just now after reading your answer I noticed that it is being interfaced with a FTDI chip. Definitely not used for power saving, I will rectify my answer just in case. \$\endgroup\$ Commented Nov 25, 2020 at 17:04
This appears to be a circuit for commanding a "reset" by momentarily interrupting the power to the PIC MCU, triggered either by the depicted switch or if the optional jumper is installed, the RTS output of the USB-UART. It's not entirely clear why that method was chosen over driving an actual reset line, but the rest of the MCU circuit is not shown; perhaps in utilized configuration the MCU lacks a reset input - documentation indicates the MCLR pin of this PIC can be reconfigured as a GPIO without reset behavior. (That this is for commanded reset and not power saving purposes is indicated not only by the control signal sources and button labeling, but also by the fact that the transistor circuit defaults to "on" and will itself consume battery-draining power when "off")
The answer to your specific question on the usage of two transistors is because the desired operational "sense" appears to be that the MCU should be powered when the control signal is high, and de-powered when the control signal is low. A single transistor has inverting behavior, so a PNP element would give the opposite of the desired operation. Thus a second transistor is needed to invert the control signal: especially in the realm of digital on-off, most non-inverting circuits are actually a sequence of two inverting stages.
An NPN transistor operating as a low side switch would have the desired logic sense, but is inadvisable to use because it would mean breaking (and possibly introducing voltage differential in) a ground connection needed as a reference for various signals going into and out of the MCU. While N-type devices are more capable than their P-type peers and passive loads are often best controlled by a low side switch, logic devices would traditionally have their positive supply switched, so that the ground side remains integral. Worth also noting that for most devices, it is prohibited to have a voltage on an I/O pin outside the range of the supply; eg, when the supply is de-powered, though there are some exceptions. Hopefully the designers took that into account, or verified that the data sheet actually does permit whatever they did...