why there is a need to define temporary reg and only then assign to the output in verilog?

Question

Following is the Verilog code for a 4-bit unsigned up counter with asynchronous clear as shown in ASIC.CO.IN:

module counter (clk, clr, q);
input        clk, clr;
output [3:0] q;
reg    [3:0] tmp;
always @(posedge clk or posedge clr)
begin
   if (clr)
      tmp <= 4’b0000;
   else
      tmp <= tmp + 1’b1;
end
   assign q = tmp;
endmodule

    

Can I define the output as reg and write the verilog as following?:

module counter (clk, clr, q);
input        clk, clr;
output [3:0] q;
reg    [3:0] q;
always @(posedge clk or posedge clr)
begin
   if (clr)
      q<= 4’b0000;
   else
      q<= q+ 1’b1;
end

endmodule

    

As I see this, there is no difference between those two codes, am I wrong?

Answer 1

There is no difference in the two examples you wrote. You can even make is simpler:

module counter (
  input  wire clk, clr,
  output reg [3:0] q
);
always @(posedge clk or posedge clr)
begin
   if (clr)
      q<= 4'b0000;
   else
      q<= q+ 1'b1;
end

endmodule

Answer 2

If it is anything like VHDL older than VHDL 2008, it is because you cannot read an output (you can only write to an output), and performing something like q<=q+1 requires you to read q.