DDR3 RAM, FPGA connection and termination

Question

I want to use a DDR3 RAM in conjunction with a FPGA. The FPGA will control the DDR3 RAM. I am using a XILINX 7series FPGA. XILINX has a guide for this, on p.129 is the needed termination mentioned, this can also be seen in below image.

Point 3 states that unidirectional signals need a 40Ohm VTT termination. And bidirectional signals need the termination at both ends. I have a DDR3 memory with an option for a on die termination. So when I use this on die termination do I still need the VTT termination?

The DQ Pins (data) are bidirectional so I will need a termination at both ends. All other pins are unidirectional, right? So they will just need a termination at the receiver side.

Answer 1

Normally the data groups (DQx, DQS, DM) have on die termination, the address and control pins however will need termination to VTT (Check the memory datasheet for details). Note that for DDR3, address and control is normally routed flyby where the data groups are point to point.

Usually the FPGA can handle the source end of the termination if you pick the correct IO banks or let the MIG do it for you, so you just wind up needing a mess of resistors to VTT on the address and control lines.

Note that the VTT plane is the reference for the impedance calculations most of the time, if referencing to other planes (Gnd) you will want extensive capacitive stitching to VTT.