LDR, LDRD and STR instructions with immediate offset in ARM Cortex-M3

Question

The Cortex™-M3 Devices Generic User Guide explains the instruction LDRD R8, R9, [R3, #0x20] as "Load R8 from a word 8 bytes above the address in R3, and load R9 from a word 9 bytes above the address in R3". I would like to ask why 0x20 equals to 8 bytes and not 32 bytes?

The guide explains the instruction LDRNE R2, [R5, #960]! as "Loads (conditionally) R2 from a word 960 bytes above the address in R5, and increments R5 by 960". Is the value or the address of R2 updated? Is the value or address of R5 incremented?

The guide explains the instruction STRH R3, [R4], #4 as "Store R3 as halfword data into address in R4, then increment R4 by 4". Is the value or address of R4 incremented?

Answer 1

LDRD R8, R9, [R3, #0x20]

I believe that is a mistake in the document. This instruction loads #0x20 (i.e. 32 bytes) above the address in R3 as you would expect.

LDRNE R2, [R5, #960]!

In this case the VALUE of R5 is incremented by the specified immediate value, 960. If you consider that an address, then it's an address. In most cases this will be an address.

STRH R3, [R4], #4

Again, as with the previous instruction, the VALUE in R4 is incremented, by 4 in this case. If you, the programmer, are considering this to be an address, then it's an incremented address.

In the 2nd two cases only the register is modified. Any memory address pointed to by these is unaffected.

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ARM Emulator