Will the Boolean equation change when we reduce the CMOS transistors in a static CMOS logic?

Question

We are doing a project about a multiplier. Two of my teammates are assigned to make the transistor level designs of the adders, subtractors and few barrel shifters. My prof has told me to make a structural level Verilog modelling of the same multiplier. He then instructed " When your teammates reduce the number of transistors for the adders and subtractors, the boolean equation changes. Put those boolean equations in the Verilog Code and we'll have the optimized multiplier". Our team is slightly confused, since the Boolean equation has nothing to do with the transistors but just the logic to be implemented.

So TLDR ; If the number of transistors in a Static CMOS logic design are reduced, will the Boolean equation change significantly?

Answer 1

Sure it does. An unsimplified boolean expression has redundant operations hidden inside it. If you implement that unsimplified boolean expression, then you will have extra logic gates/transistors implementing those redundant operations.

If you did things correctly, the end result doesn't change, but the path to get there does.

the Boolean equation has nothing to do with the transistors but just the logic to be implemented.

The boolean equation is used to pick the logic gates, and the logic gates are made of transistors.