How can I avoid "Minimum Pulse Width" slack violations in Quartus FPGA synthesis?

Question

I am synthesizing a toy application on DE2, but I hit a timing problem (despite every inputs and outputs are clocked in my design). These violations are related to "minimum pulse width"...

How can I avoid such negative slack during FPGA synthesis ?

+----------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLOCK_27'                                                                     ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                     ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------+
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; HEX0[0]~reg0  

Answer 1

I think pjc50 has the right idea; have you edited the .sdc file "create_clock" statement? it has a "waveform" keyword that gives a rise and fall time for the clock waveforem, and the above can happen if these are too close together (e.g. "{ 0.000 1.000 }"). Not to belabor the obvious, but it should be more like "{ 0.000 18.519 }" for a 50% duty cycle and a 27 MHz clock.