Minimizing pulled open collector output rise time on 74LS09

Question

I have a circuit that calls for one open collector buffer for driving a shared line (/WAIT via Zilog Z80) and one typical AND gate. I've consolidated these into a single 74LS09 open collector quad 2-input AND gate IC.

To make the "typical" AND gate behave typically, I assumed something in the range of 10K to 1K would suffice for a pull-up resistance, but my tests are telling me something else. My oscilloscope sees a rise time of 2.4 microseconds at 10K, and 250nS at 1K. If I cut it down to 320 it still takes 92nS of rise time.

Referring to: https://www.ti.com/lit/ds/sdls034/sdls034.pdf I was surprised to see the rise time T_PLH on page 4 with 2K resistance should be around 35nS. The best I have achieved is around 500nS. In comparison, the fall time I've measured is around 17nS and hasn't changed much between tests.

As you've probably detected, I'm not incredibly familiar with this domain. Does anyone know what knowledge I may be missing? If there is more context I can add about the test circuit please let me know.

Additional context:

• My unused inputs are all tied low
• My LS09 will be used in a circuit that is clocked at 1MHz, so it needs to be a bit snappy
• All logic is at 5V
• Adding 10pF of capacitance to output against 5V or ground did not impact results
• Decreasing input rise time did not impact results
• These LS09 chips were bought on Amazon (https://www.amazon.com/gp/product/B08CCD472L), and were shipped in an antistat bag
• Multiple LS09 chips respond the same way, although all are from the same seller

Answer 1

10% to 90% rise time is approximately 2.2RC so with your 10K pullup a 2.4usec rise time implies around 110pF load. Assuming you used 10% to 90%.

If we check the datasheet for the RP2200 Rigol probe:

That's pretty much what we would expect.

In general, for more than a few MHz, you almost always want to use the x10 position on your probe.

This also illustrates graphically how open-collector (or open-drain) + pullup gates can cause rise time problems with even moderate capacitive loads.

Answer 2

There are different ways to measure risetime.

• risetime Tr=RC is 0 to 63%of V which also is approximately the linear asymptote of the initial slope to V+ so 1k*30pF = 30ns
• but usually one measures risetime from 10% to 90%. Which is a bit bigger since it spans 80%
• but for TTL the time is from 0 to 1.3V the typ. threshold to activate the inverter then latency internally is included in the output delay

The are better ways to speed up TTL using Thevenin V=2V with pull up/down ratios and use less current. In the early days of 68000 CPU’s active terminators with smaller R doubled the speeds with adequate margin. Early SCSI also used this.

Then of course 74HCTxx CMOS logic with smaller junctions is even faster, and much lower high level impedance drivers (50 ohms) which goes even faster moving from 5.5V logic to 3.6V logic families (<25 ohms) then surpassed by current mode logic CML like ECL the older namesake.