H-Bridge chip burning up when applying less voltage than the absolute maximum

Question

I have a circuit that allows me to automatically control my blinds by having a H-bridge chip control a small motor, usually 12V.

The full schematic can be found here.

I have now tried to use the same circuit (as I had them hanging around) to control a 20 V linear activator. I have destroyed a few hbridge chips now but have determined when powering my circuit with 15V the H-bridge chip burns.

The chip is a ZXMHC3F381N8

The data sheet Absolute maximum ratings says

Gate-Source voltage VGS ±20 ±20 V

What am I missing here ? Why does 15 V kill it ? (This is with no load connected by the way)

Ideally I would like to control the gate with a lower voltage than the supply voltage but I only wanted one regulator on board with is a 3.3 V and that's not enough.

Maybe a voltage divider where I can customise the resistors for different applications but that sounds clunky.

Any suggestions for that ?

Answer 1

The circuit is flawed and as pointed out already you have gate drive current problems for the opto-isolators. The datasheet for the part used shows no speed characteristics, but the Sharp part it is copied from shows 3-18us rise/fall times at 2V VCE, it will be much worse at 12-15V. This slow rise and fall time guarantees you will have both FETs on for a period of several microseconds.

In addition, if you are driving the opto's from an MCU it's likely that you can end up with all four FETs turned on for periods depending on how fast you switch the MCU output ports.

Fixing the pullup resistor for the opto's will not overcome the poor design and you may still see failures.

To solve the problem properly you need to drive the upper and lower FETs using their own signal drive, AND guarantee there is an appropriate OFF time for both FETs (and both sides of the H-bridge) during switching.

Answer 2

My best guess is you are switching the gate voltages too slowly.

As the gate voltage switches from high to low (or vice versa) there is a time when both the PMOS and NMOS FETs on one side of the bridge are active, and high currents can flow through them. If the transition time is too long, this produces enough heat to burn out the FETs.

This becomes a bigger problem as your supply voltage increases, first because it means a wider range of gate voltages that will activate both FETs. With 2 V threshold voltage on the NMOS and -2 V on the PMOS, and 12 V supply, any gate voltage between 2 and 10 V will allow substantial current through both FETs. With 15 V supply, any gate voltage between 2 and 13 V will do so.

In comments you added:

The voltage to the optocouplers is 3.3v from the GPIO pins on the ESP.

This is more likely the cause of your problem. With 3.3 V input and 1.2 V forward voltage on the opto, you have about 2 mA into the optocoupler input. Your IS357B has CTR between 130% and 260%. Say it's nominally 200%, then you have 4 mA output from the opto. Pulled through the 1 kohm resistor at R11 or R12, that only drops 4 V, giving you a maybe 11 V at the H-bridge gate. Which is well in the range to blow out the H-bridge.

You need to increase R11 and R12 to at maybe 8 or 10 kohm for operation with 15 V supply. But be careful that a higher resistor value doesn't lead to slower rising transitions, which could again over-heat the bridge.

Answer 3

Using Opto couplers to drive the Gates at 10V is needed to make use of the low RdsOn. You can use two resistors to scale Vcc from collector to gate, if using more than 12V or a series R and 15V to 18V

• if you don’t create a skew in the timing for a deadtime or at least 10 to 50 ns the bridge is shorting out the supply.
• Normally this is done with slow rise time with a series gate resistor (10 to 100) into Ciss and for low level a diode with low resistance to turn off faster than the other turning on. Thus break before make.
• This in turn creates a voltage spike into a clamp diode or snubber or the body diode of your FETs.

These are designer choices to use the bridge properly.