MOSFET symbol - direction of source terminal

Question

There are two possible illustrations of MOSFETs : with an arrow, and without an arrow.

example for NMOS with arrow :

example for NMOS without arrow :

example for PMOS with arrow :

example for PMOS without arrow :

For case of schematic with arrow, I could make a 180 degrees rotation without any problem : I will still recognize the source and the drain.

For the case of the schematic without arrow, I have no more way to recognize where is the source.

So my question is : for the schematic without the arrow, is the source of NMOS always at the bottom, and is the source of the PMOS always at the top ?

Answer 1

If the source and drain are not marked in some way then you would assume that the device is symmetric, meaning that the source and drain can be interchanged and neither is connected to the substrate.

In this case, the terminal that is lower in voltage will be the source for an NMOS transistor and the terminal that is at a higher voltage will be the source for a PMOS transistor. \$V_{GS}\$ is always measured with respect to the terminal that is acting as the source.

And, yes, the roles of these two terminals can be swapped in real time as the voltages change. That can happen in a CMOS transmission gate, for example.

Answer 2

A four-terminal MOSFET, such as a typical one seen in a VLSI (integrated circuit) realization, is mostly symmetric, and its source/drain are established by the relative voltages on the two terminals that connect to the channel. An NMOS device, fabricated by implanting two N-regions in a p-well or p-substrate, has its source at the N-implant connected to a lower voltage. A pMOS device, fabricated with P-implants in an N-well, has its source at the P-implant experiencing a higher voltage.

This is not necessarily static either - in a transmission gate, the relative voltages of the two ends may change sign during circuit operation.

In discrete realizations, the device is no longer symmetric because one of the two ends of the channel is designated the source and is bonded to the body, creating a parasitic body diode structure. If the relative voltage of the source and drain is "wrong" (i.e. nFET having source voltage > drain voltage), the body diode will conduct.

Answer 3

Context matters. In the context of CMOS logic designs (which is often where you find these seemingly ambiguous symbols) it is understood that VDD is on top, VSS is on bottom. Also, PMOS sources are tied to VDD and NMOS sources are tied to VSS. The drains of both PMOS and NMOS are tied to the output(s) of the gate or logic stage. The body diode connection is not shown. PMOS is distinguished from NMOS by having a "bubble" at the gate input, indicating that output (drain) has opposite polarity of input (gate).

I agree with the other answers as general answers, where context is not accounted for. But I wanted to just provide this additional comment about the context of CMOS logic designs.

PMOS, when on (gate low) pulls the output high. NMOS, when on (gate high) pulls the output low. That is just how CMOS logic works.