Can my digital wave synthesizer clock be different than my DAC frequency?

Question

I'm using an FGPA to synthesize and output a sine wave at ~6Mhz. I noticed that if I crank the clock in the DDS compiler (Xilinx Vivado) up to about 100Mhz or higher, the wave appears very nice in my simulations.

Does this mean my DAC needs to be 100Mhz as well in order to be synchronized with the DDS Compiler?

My simplistic understanding of DACs is that if it says it runs at 20Mhz, then a voltage level, based on a binary input (R2R design), will be outputted once every 50ns and would not work with the DDS which would output a value every 10ns.

And would I have the same issue if I wanted to feed the signal directly back into the FPGA using an ADC operating at the same frequency? I believe I shouldn't because of Nyquist's theorem but my understanding of signal sampling and reconstruction is pretty shallow.

Will someone help me reconcile this?

Answer 1

The Nyquist rate for a 6MHz signal is 12MHz (12 Msamples/sec.) With a perfect reconstruction filter, you could in theory use just 12MSPS to represent the signal. In the real world, such a filter would be difficult to realize owing to the steep roll-off needed (high order, etc.) so it is helpful to 'oversample' the output so the reconstruction filter can be more gradual (reduce the filter order.)

As it is, the bandwidth you're working with (6MHz) is similar to legacy (PAL, NTSC, SECAM) video. Video encoders will typically use 27, 54 or even 108MHz to drive the DAC and will use an upsampling filter to create more samples. The higher the final sample rate, the smoother the signal (less out-of-band aliasing), and thus, the simpler the reconstruction filter can be.

With your setup what you're effectively doing when you 'crank the clock in the DDS compiler' to 100MHz is to create larger tables with more samples. The table creation process uses, you guessed it, an upsampling filter, to create waveform tables at 100MSPS. This could also be realized in line as an FIR filter, working on a base 12MSPS data stream.

Either way, at 100MHz (100 MSPS) you're doing about an 4x upsample to create your clean signal. This works out if your DAC can accept 100MHz samples. If your DAC can only sustain lower frequencies, you will need a better reconstruction filter to get a good, clean signal.

One more thing: the upsampling filter and / or the reconstruction filter needs what's called zero-order hold or sinx/x correction. This compensates for the difference between a typical DAC stepped waveform and a stream of sample points with zeroes between them.

Answer 2

You are correct - if your DAC is only good to 20MHz, then it is not a good idea to exceed this. Thus your DDS can only output at the DAC’s rate.

Your 6MHz output is going to look pretty crappy if your DDS clock is 20MHz as you only have 6.6666 samples per cycle. An analog filter on the DAC output would clean that up.

Similarly for the ADC, if it is giving 20msps, its no use reading it any faster.

That doesn’t stop you doing processing at a higher clock rate - ie filtering might take a number of clocks, so that could be done at greater than 20MHz.

Answer 3

Your DAC chip has a maximum sample rate specification (check datasheet). If you overclock it, it will probably behave the same as any other digital circuit under such circumstances. In order of increasing clock frequency, it will probably work fine a bit above its spec (but with no guarantee), then begin missing some bits once in a while as the slowest path inside the chip gets overwhelmed, then miss some bits more often, then output complete garbage. It depends on temperature, supply voltage, etc, so just because "it seems to work today", doesn't mean you can count on it.

Note the internal clock of the DDS generator may run higher than the DAC sample rate. That depends how it is implemented. For example you may be able to use less FPGA gates by using a DDS that needs several clocks to output a sample instead of one, so it can use only one multiplier instead of several in parallel. Then you have two clocks, a faster one for the core that computes the sample, and a slower one for the actual DAC sample rate.

How fast your DAC should be really depends on how clean you want your output 6MHz sinewave to be. Fs=20MHz sample rate for a F=6MHz sine wave is 3.33 samples per period, which is really low. In the time domain, the output will not look much like a sine wave. In the frequency domain, there will be substantial aliasing products at nFs-F and nFs+F. This means you will either need an annoyingly complicated analog filter to get a usable sine wave, or an application that doesn't care about the aliasing products. In fact, with only 3.33 samples per period, it would probably be simpler to just get rid of the DAC, output a square wave, and filter it, but then you lose the fine frequency adjustment that DDS offers.

If your application needs a cleaner sine wave, then... you need a DAC with higher sampling rate, or a DDS chip, whatever is cheaper. Remember the total cost includes analog output filter, so a faster more expensive DAC may end up cheaper if you can replace a complicated filter with a simple one.