What are the length and width specifications for PMOS and NMOS transistors and capacitor ranges for 90 nm CMOS technology? I'd like to design a low power full adder cell using majority charge function.
(Majority charge function: If more than half of the inputs are 0, then the equivalent input given to the inverter is 0, if more inputs are 1 then its equivalent input is 1.)
The only specification for a 90 nm technology is that you should be able to make a transistor with a minimum gate length of (wait for it..) 90 nm.
These parameters are fairly specific to each manufacturer and are usually considered trade secrets. Depending on where you're looking, you might be able to get access to a foundry's technical documentation for research purposes, but you will be signing Non-Disclosure Agreements.
Since it doesn't seem like you're actually wanting to fabricate a chip, I would suggest using Predictive Technology Models. These are SPICE models that are basically generic (not process specific) transistors for a given process node. ASU publishes these models for public use, and since they are not tied to a manufacturer a NDA is not required (but don't forget attribution!).
Taking a look at the 90 nm models, you can either use the full models and simulate to your heart's content, or you can start digging through the models to extract a capacitance. To estimate capacitance, we can simplify the transistor's gate to be a simple 2-plate capacitor separated by the gate oxide. Using the capacitance formula, we get the following:
\$ C=\varepsilon_r\varepsilon_0\dfrac{A}{d}\$
and we'll rearrange it so that we can solve for a capacitance per unit area.
\$\dfrac{C}{A}=\dfrac{\varepsilon_r\varepsilon_0}{d} \$
where \$\varepsilon_0 \approx 8.854 \times 10^{-12} F\cdot m^{-1}\$
The parameters that we're looking for are the thickness of the gate oxide, tox or the effective oxide thickness, toxe; and the dielectric constant \$\varepsilon_r\$, epsrox. Looking at the NMOS device, the model lists toxe = 2.05e-9 and epsrox = 3.9. Plugging these values into our equation, we get:
\$\dfrac{C}{A}=\dfrac{\varepsilon_r\varepsilon_0}{d} = \dfrac{3.9 \cdot 8.854 \times 10^{-12} F\cdot m^{-1}}{2.05\times 10^{-9}m} = 16.84\times 10^{-3}F\cdot m^{-2}\$
For a minimum-sized NMOS transistor, we know that L = 90 nm, and we can assume that the minimum W is about the same, so our transistor's gate capacitance would be calculated as:
\$ C = W \cdot L \cdot \dfrac{C}{A} = 90 nm \cdot 90 nm \cdot 16.84\times 10^{-3}F\cdot m^{-2} = 136 \times 10^{-18}F\$
These figures are useful for first-order approximations, when you need a ballpark figure. These capacitances are non-linear and we are neglecting fringe effects, so your mileage may vary. For classroom assignments, I would think it's fine.
