I'm trying to configure a Memory Interface Generator IP in Vivado. Somehow, the Block Automation doesn't work and I've to do it myself.
The board I'm using is the Arty A7 development board. It has a DDR3L SDRAM on it. The reference manual of the board states that the data width of the external memory is 16-bit. I also checked the schematic and saw that there are 16 pins for data transfers. See below.
Does the data width of an external memory is the same as the pins/lines used for the connection? What is the limit for it? From which part of the memory part datasheet can I determine this data width thing?