In a typical ASIC design cycle, how much time is taken by an EDA tool to complete the routing? Assume a fairly complex chip (like the Ivy Bridge). I've heard the entire chip design cycle is typically an year or so, what I want to know is the time taken for the routing (or placement & routing). I was told that it is of the order of several weeks, so I wanted to verify with someone who has some industry knowledge. :)
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Routing or PNR takes the longest time as they have to match the timing. It usually finishes the last as they are the recipient of all the chip blocks (typically from various departments). Once all the blocks are received they make sure that the blocks are placed optimally so that the timing is met.
The team also generates huge data (~700GB in my case per scenario). Once the best timing is achieved other scenarios are removed and best one is kept.
The team may also have to do an IR drop analysis so that every part of the chip gets enough current.
answered Feb 22, 2013 at 7:56
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\$\begingroup\$ Thanks for the answer! Could you also tell me approximately how much time does routing take in a typical development cycle? I understand there is no best answer since it depends on several other factors, but what could the approx time be given a complex chip like an Ivy Bridge processor? \$\endgroup\$– tecfreakCommented Feb 22, 2013 at 9:10
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\$\begingroup\$ @tecfreak the time taken depends on the kind of chip, timing requirements, etc. In out case it took around two months to close the timing. \$\endgroup\$ Commented Feb 22, 2013 at 9:12
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1\$\begingroup\$ @Chetan : it is my perception (as an avid DeepChip reader with only FPGA experience) that an actual run through P&R takes hours (maybe 24) rather than months : it's the iterative nature of fixing failures (timing, IR, crosstalk etc) that stretches to months - is this correct? \$\endgroup\$– user16324Commented Feb 22, 2013 at 10:58
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\$\begingroup\$ @BrianDrummond our chip involved HS SerDes and embedded memory. I'm not sure why they took much time. \$\endgroup\$ Commented Feb 22, 2013 at 20:08
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1\$\begingroup\$ @BrianDrummond That is consistent with my experience \$\endgroup\$– W5VOCommented Apr 2, 2013 at 3:59
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A cutting-edge chip like Ivy Bridge is probably not routed all at once. It is most likely broken down into chunks, and thus built in pieces to keep run time within manageable limits. Routing the full chip would doubtless take weeks or months, depending on the difficulty of the constraints.
How much time does a chunk take to route? Well, the chip will be divided such that run time is "acceptable". What is "acceptable" will be a function of how many iterations are needed to close timing.
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The big ASIC chips are usually broken down into pieces and implemented separately. After that we integrates the blocks. So there is no point thinking about the full chip route time . In my company the blocks (large blocks) takes around 24 to 30 hours . We accomplish timing closure through different iterations. Thats why it whole design process taking lot of time
