Addition of two hex numbers in Verilog gives wrong result

Question

I am trying to add hexadecimal numbers in Verilog but I am getting the wrong outputs.

Here are the numbers I am adding. Variables temp_1 and temp_2 are both defined as follows:

reg [0:31] temp_1;
reg [0:31] temp_2;

The addition is defined in Verilog as:

temp_1 = 8'hb7e15163 + 8'hb7e15163;
temp_2 = 8'hb7e15163 + 8'h0c0d0e0f + 8'hb7e15163; 

Here is the output I am getting from the simulator:

I thought the outputs should be temp_1 = 16FC2A2C6 and temp_2 = 17BCFB0D5

What am I missing? Is the simulator chopping off the output?

Answer 1

You’ve declared your constants as 8 bit values with the 8’ prefix. So 0x63 + 0x63 = 0xc6 which is correct. If you want a 32 bit result then use the 32’ prefix on your constants.