I'm finalizing the routing for an eighteen-layer board that requires many, many differential-pair traces to run at speeds up to 16 Gbit/sec. (FYI: 100 Ω impedance, Isola I-Speed cores and prepreg.) These traces come from an MPSoC (BGA) with TX/RX pairs at 100 Ω impedance. All vias must be through-hole.
My design constraints limit me to roughly 3 mil trace gap while routing under the MPSoC due to the through-hole vias, then spread out to roughly 6 mil when the trace gap is no longer limited under the MPSoC.
I'm having trouble deciding whether my differential-trace pairs should spread out suddenly or gradually. I've read that in high-speed designs, trace width (not trace gap) will gradually fan out right before a pad to the pad width in order to minimize the sudden impedance change, similar to a tear-drop effect. Though taking this notion and extending it to trace gap seems logical, it poses two questions:
Is this reasoning even correct? A specifically unnamed eval board with trace pairs running at much higher bandwidth than mine (see below) employs a "sudden" gap-change, regardless of whether the trace pairs are A) "regular" high-speed using 45° bends, or B) "super duper" high speed and requiring curved traces.
What is too large of a differential-trace pair length to be changing the gap? If my reasoning is correct, there is no maximum "change in gap" length, but this doesn't feel right intuitively.
Here is an example from the aforementioned eval board, with the sudden trace gap-changes circled in red.
Here is an example of my board, with sudden changes marked in blue and the gradual changes marked in green.
Could someone please advise on the better strategy for this situation and explain why either the sudden gap (ergo, impedance) change or the gradual gap (impedance) change works better?