A single read actually reads an entire row (usually something like 2 or 4kbits) at once, selected by the Row Access Strobe (RAS), addressed to one bank. But you're not done yet, all this data is still within the DRAM chip.
What data you select from this row depends on how you use the Column Access Strobe(CAS), the DRAM generation, and how you initialised it. To get 64 bits on a x8 wide device, you'd use a burst length of 8, on most modern (DDR-n) SDRAMs, which are aimed at systems with cache memories, so that the burst length is aligned with the L1 cache line size.
Access patterns supplying all 2kbits require Page Mode, where repeated CAS strobes keep supplying successive data until either a Burst Terminate or Precharge command. Page Mode, unfortunately, hasn't been seen in years (outside of special graphics memory devices which may or may not still exist).
I think the last DRAM generation to support Page Mode was (SDR) SDRAM circa 2000, and it was dropped with the first (or maybe second) DDR generation. Which is a pity, because Page Mode was great for streaming vast amounts of data through a custom processor on an FPGA. (You can mimic Page Mode via a carefully timed sequence of short bursts, but it's much less convenient)
Banks come in by allowing multiple Row accesses (max. one per bank) to be in progress at once. Having accessed a row in one bank, you can leave it open (for a while, like 8 ms or one refresh period) while also accessing a row in another bank. Which is great for allowing things like copying data from one array to another (perhaps via some intermediate processing stage) by reading from one (or more) banks and writing to another.
