Build on-chip ROM in HDL

Question

I wrote the next code in quartus 15.0, where I show what I want to do for a specific project. I can write it both in VHDL and Verilog HDL, but verilog is notoriously shorter.

module TOP(
    //
);
//
ONCHIP_RAM_verilog #(
    .ADDRESS_WIDTH (16),
    .DATA_WIDTH (64),
    .INIT_FILE ("FIS_ROM.mem")) //ANY FILE
u_rom(
    .CLK            (CLK),
    .WRT            ( ),
    .ADDRESS        (my_address),
    .DATA_IN        ( ),
    .DATA_OUT       (my_data)
);
endmodule

module ONCHIP_RAM_verilog #(
    ADDRESS_WIDTH = 8,
    DATA_WIDTH = 8,
    INIT_FILE = "MEM.mem")
(
    input wire CLK,
    input wire WRT,
    input wire [ADDRESS_WIDTH-1:0] ADDRESS,
    input wire [DATA_WIDTH-1:0] DATA_IN,
    output reg [DATA_WIDTH-1:0] DATA_OUT
);

//THIS WON'T BE BUILT IN THE ON-CHIP MEMORY,
//BUT WITH LOGIC ELEMENTS INSTEAD
//initial begin
//  $readmemh (INIT_FILE, my_mem);
//end

//BECAUSE I AM USING A MAX 10 FPGA
(*ramstyle = "M9K"*)reg [DATA_WIDTH-1:0] my_mem [(2**ADDRESS_WIDTH)-1:0];
// /*synthesis ramstyle = M9K*/; other option

always@(posedge CLK)begin
    if (WRT)begin
        my_mem[ADDRESS] <= DATA_IN; //write
    end
    DATA_OUT = my_mem[ADDRESS];     //read
end

endmodule

Where I define my simple module/entity ONCHIP_RAM, which in normal circumstances -as a RAM- works perfectly fine, I define its size in the TOP module and it stores data normally. If I would like to build a ROM, I could easly not use the WRT and DATA_IN wires, but the initialization from the file INIT_FILE won't build the on-chip memory, instead it will build my ROM from logic elements, and as I need larger rom's my resources get limited.

I know I can build a ROM in the Qsys tool from Quartus, but I would really like to use HDL only because my project can easly change from an altera to a xilinx dev board. This is also true for the altsyncram file which bassically solves my problems, because I did some tests with that file, but I doubt it will work on ISE or Vivado.

I also get message 276014 and (276013): RAM logic "ONCHIP_RAM_verilog:u_ram_verilog|my_mem" is uninferred because MIF is not supported for the selected family which does not appear when I use Qsys and the altsyncram file, for which I think quartus does write the on-chip rom in the programming file, meaning part of my problem might be with the software configuration.

I hope you could help me and thanks in advance.

Answer 1

Taking a step back, the simplest solution to implementing ROM (a) using Block RAM, not LUTs, and (b) allowing switching between different compilers and target FPGAs is to use a component.

Define your ROM as a separate Verilog entity/component (using VHDL terms), say MYROM. Then produce two MYROM design files: one for use in Altera Quartus, one for Xilinx ISE.

Each MYROM file instantiates that manufacturer's primitive for a ROM with any memory initialisation file (in Quartus, a MIF file). Both the Quartus and ISE projects need their source files specified to them, so each will simply call up its specific MYROM file.

This use of a 'wrapper file' is pretty standard. By not implying the ROM in Verilog, you remove the possibility of the compiler not inferring it correctly from the source file and trying to make the ROM out of LUTs instead.