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Introduction: I made a PCB with Allegro that is made of three layers. The mid-layer is completely the RF ground, and the bottom layer is connected to the connector so it is all ground as well. enter image description here I have two types of through vias that are all plated.

Problem: I noticed that the small size vias have no mark on the mid-layer Gerber files, but they are marked in the top layer and bottom layer. The big vias however have marks in all layers. As far as I checked it goes back to the via definition. My question is that: Are the small plated vias connected to the mid-layer when the PCB is fabricated or not?

As requested, I include a screenshot of the vias as well. The vias that I thought are the problems are shown (the small vias). However, the bigger vias that are defined well, as my colleague told me, are not shown (I do not know why)

enter image description here

I also included the via definition if anyone is an expert in this matter

The bigger vias that have marks in the mid-layer

The smaller vias that have no marks in the mid-layer

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    \$\begingroup\$ Can you show a screenshot (cropped or highlighting the via of interest) of the Gerber files themselves, as viewed in the viewer you were using? \$\endgroup\$
    – nanofarad
    Commented Jan 31, 2022 at 14:49
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    \$\begingroup\$ Just a note, have you verified the fab can make 3-layer PCB's? They might want to convert it to a standard 4-layer board. \$\endgroup\$
    – rdtsc
    Commented Jan 31, 2022 at 15:45
  • \$\begingroup\$ @nanofarad Added. \$\endgroup\$
    – NightElf
    Commented Jan 31, 2022 at 15:45
  • \$\begingroup\$ @rdtsc Yes, they can. The test structure is just made to measure the RF filters. Unfortunately, the filter response is very far from simulation. One of the problems could be that the RF ground is not well made enough. When I was checking the Gerber files and drill files, I noticed that there are differences between my vias definition. Because all the holes are plated I thought it would not be a problem. Now after measurement, I have some doubts. \$\endgroup\$
    – NightElf
    Commented Jan 31, 2022 at 15:51

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In gerber files, vias typically aren't specifically marked at all.

They only exist as a coordinate in the drill file (and possibly in the drill information file if you add one). Then the PCB manufacturer will through-plate any hole that is directly connected to copper.

Many CAD softwares show holes when you are drawing the PCB, exactly how they are shown varies depending on settings and CAD suite. But in the gerber files, they don't exist until the PCB manufacturer drills a hole through the copper using the information in the drill file. For vias, they drill through the copper, they don't (nor you or your CAD software) remove the copper where the hole is going to be.

Although, non-plated through holes should have the copper removed where the hole is going to be, with some margin. Otherwise you might get exposed copper sticking into the hole.

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  • \$\begingroup\$ Correct. Sorry, I usually make GERBER FILES and drill files. Can I say that the small holes are definitely connected to the mid-layer? I am asking this question mainly because the small holes across the board are there to make the mid-layer a proper RF ground. If those vias are not connected to mid-layer then I made a mistake. \$\endgroup\$
    – NightElf
    Commented Jan 31, 2022 at 15:41
  • \$\begingroup\$ Holes to be plated are marked "Plated Through Hole" (PTH) in the drill file. They are plated (as in electroplated) after drilling. The manufacturer should tell you if you designed a feature they cant produce reliably. You should expect your board to match your 3D model/visualization. \$\endgroup\$
    – crasic
    Commented Jan 31, 2022 at 15:53
  • \$\begingroup\$ IME you typically need to supply two entirely separate drill files. One for plated and one for unplated holes. Because they are drilled in entirely separate operations. The unplated holes aren't drilled until after the plating step is done. \$\endgroup\$
    – The Photon
    Commented Jan 31, 2022 at 15:58
  • \$\begingroup\$ If a via is connected to a solid internal plane instead of a pad, often you won't see anything on the Gerber. One way to convince yourself that everything is still ok is to temporarily change your via definition use thermal relief on intermediate layers, this feature will make the holes very obvious on the layer file as well. \$\endgroup\$
    – crasic
    Commented Jan 31, 2022 at 16:01
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    \$\begingroup\$ @NightElf Unless there is copper removed around the hole, and you specify the holes to be plated (may need to check with your PCB manufacturer how they want you to differentiate plated vs. non-plated holes as others has mentioned, most commonly they will plate all holes connected to any copper if you don't specifically specify otherwise), you can be sure they will be connected to the mid-layer. \$\endgroup\$
    – Klas-Kenny
    Commented Jan 31, 2022 at 16:52

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