Is the L298N H-bridge in FPGA (Intel DE0-Nano-SoC) compatible?

Question

I am trying to write a code that controls various DC-motors through a multi L298N H-bridge using FPGA (Verilog or VHDL). I have a PWM signal generated right now, but can't figure out how to write to the M1/M2/M3/M4 of the driver. I wanted to know how I would go about doing this, what my pin assignments would be etc. Any help is appreciated.

Link to the H-bridge: https://www.robotshop.com/ca/en/multimoto-4-channel-h-bridge-speed-controller-arduino.html

Sorry to further clarify, I needed to know how to send the PWM signal to the specific M1 motor interface to drive it

Answer 1

Starting with the connectivity - you will have to interface the external board according to its rules.

It seems the referenced controller board exposes 4 independent channels to control motors. So in general case of controlling all four motors independently you will need four parallel PWM outputs, so 4 identical PWM cores should be instantiated in FPGA.

How exactly you will control each PWM core - this depends on your design needs. You might organize your PWM cores as peripherals on internal bus (Avalon is typical for Intel/Alter) and expose that bus to ARM cores via lightweight HPS-to-FPGA bridge. Each PWM input register then would be an individual location in the memory area that you will map into your application's address space, and then you control motors with software by writing the speed/direction value(s) at the specific offset from the base of the mapped memory area.

Or maybe handling the values for PWM inputs will stay entirely inside the HDL design - this is for you do decide, and you didn't indicate the way you intend to implement the system as a whole.