I recently saw a circuit that left the NMOS's source open without connecting to any terminal.
Gate: A pull-up 10 kΩ resistor to 3.3 V.
Drain: A pull-up 10 kΩ resistor to 3.3 V.
Source: Nothing connected.
The source has a fixed 2.2 V observed by the oscilloscope.
The MOSFET's Vth is 1 V (min.) to 2.5 V (max.) according to its datasheet.
I varied the gate pull-up voltage source from 3.3 V to 2.5 V and 4 V and the voltage on the source side became 1.5 V and 2.9 V. It seems to me the voltage on the source is Vgate minus Vth(min).
Does anyone know why the source is left open but still has a fixed voltage level?
*I attached the circuit in the below. I removed R38 & R36 and still see Vsource = 2.2V as stated above. Q7 is the N-MOSFET. *There is a Pull-up resistor (10K) placed in other page for PCIE_SMCLK & PCIE_SMDAT.