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I want to use a PCM5242 DAC (datasheet) in a project

The DAC has a built in DSP core that I don't want to use for anything custom.

The DSP can be programmed with custom code, or predefined codes in the chip's ROM can be used.

Program Selection

For normal operation at various sample rates I want to use the default program 1 which is a interpolation filter that can be configured to allow x8/x4/x2/x1 oversampling for the DAC. According to the table the DSP needs 256 cycles for this filter per sample, which means, the DSP frequency has to be at least 256 times the sample frequency.

On page 119 the datasheet shows examples on how to configure the clock tree in the DAC for various sample rates and an externally provided system clock. This is my intended application.

Clock settings

I want to use 192 kHz and 384 kHz sample rates at an SCK frequency of 24.576 MHz.

First Case: 192 kHz Operation

According to the datasheet, for 192 kHz a 2x oversampling is used internally (which means I need an interpolation filter).

The first line in the table shows this case. I understand where the prescalers for the OSRCLK and the DACCLK (DOSR and NDAC) come from. However, I don't understand, how the DSP frequency is calculated.
The table lists a DSP Frequency of 24.576 MHz (=SCK), which is only 128 times the sampling frequency. So according to table 7 (see above), this is not enough to run the interpolation filter.

I know, that I can simply configure the PLL in the PCM5242 and generate a 256 times 192 kHz clock solely for the DSP which essentially is still in range of the clock spec․ and would work as far as I see.

However, the datasheet explicitly lists the lower DSP frequency. How is this possible?
Do I need to write a custom program for the DSP in that case? (Which I want to avoid because I simply want a DAC.)

Second Case: 384 kHz Operation

In 384 kHz Operation the case is similar. No matter how the device is clocked, the DSP will at most run at 49.152 MHz (128 times the sampling frequency) which is too low for the interpolation program. I'm aware that I don't need an interpolation filter for 384 kHz operation, since the oversampling is x1. However, the DSP program cannot be disabled, as far as I see. A program is always active.

How to use the DAC with this sample frequency?

TL;DR

The DSP in the PCM5242 requires a clock frequency of 256 times the sampling frequency when using program 1 but this is outside the limit for the PLL at 384 kHz sample frequency. How to configure the DAC?

Do I need a custom DSP code for these cases, which will need fewer cycles?

I've been looking in the datasheet for several hours but really couldn't wrap my head around the problem.

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  • \$\begingroup\$ It is designed for 384kHz so my guess TI should have sufficient documents to support that \$\endgroup\$
    – D.A.S.
    Commented Apr 3, 2022 at 17:03
  • \$\begingroup\$ Unless I am missing something (did not read the entire 100+ page datasheet), setting an interpolation filter to x1 disables it, meaning the delay is zero. Probably the minimum delay figure refers to the case that the filter is running while ignoring the disabled case, otherwise the minimum delays would always be zero. \$\endgroup\$
    – user1850479
    Commented Apr 3, 2022 at 17:05
  • \$\begingroup\$ not much latency in 384kHz for audio at x1 \$\endgroup\$
    – D.A.S.
    Commented Apr 3, 2022 at 17:15
  • \$\begingroup\$ Let me rephrase the question: What is the minimum DSP frequency for 192kHz and 384 kHz sample frequencies? I don't see any information in the datasheet except for the cycle number given in the table. \$\endgroup\$
    – GNA
    Commented Apr 4, 2022 at 14:57
  • \$\begingroup\$ Whether DOSR or EIFM 1 disables interpolation: ask in the TI support forum? \$\endgroup\$
    – greybeard
    Commented Apr 17 at 6:23

1 Answer 1

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I want to use 192 kHz and 384 kHz sample rates at an SCK frequency of 24.576 MHz.

If you want to run the DAC at 384kHz and the DSP at 49.152MHz, then should work:
Have SCK (input clock) be 49.152MHz
Divide the SCK by 128 to get a DACCK of 384kHz by setting register DACCK to 128.

If you want to run the DAC at 192kHz and the DSP at 49.152MHz, then should work:
Have SCK (input clock) be 49.152MHz
Divide the SCK by 128 to get a DACCK of 384kHz by setting register DACCK to 128.

enter image description here Source: https://www.ti.com/lit/ds/symlink/pcm5242.pdf

Since the largest divider for DACCK

Here is the clock tree for running DSPCK 256x above DDAC and DDACK at 192kHz, however this requires the PLL and selecting SCK for the DDACK.

enter image description here However, you need a different starting clock so there isn't a way to switch between the two without changing the starting clock.

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  • \$\begingroup\$ This doesn't really answer my question. If I clock the DSP on 48.152MHz and use 384kHz sample rate, the DSP is clocked at 128 times the sample rate, which according to tbale 7 in the datasheet is too low. They explicitly state a minimum cycle count for the DAC program to be 256 cycles. \$\endgroup\$
    – GNA
    Commented Apr 17 at 13:14

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