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Regarding my previous question and this paper, I wanted to simulate the circuit below to see whether it is rejecting common mode voltage as claimed. The paper says that sharing DAC's Vref with non-inverting node, the common mode voltage variation at Vref will not effect the output:

enter image description here

To try that, I first modeled the DAC and tried the following circuit in LTspice:

enter image description here

But I get the following plots for (Voutp - Voutn) and Vcm; showing that Vcm appears at the output:

enter image description here

Another similar variant of this circuit is as follows(with voltage divider):

enter image description here

And now I removed the ground of the DAC model and voltage divider to the non-inverting input as follows:

enter image description here

And now the output is quiet small:

enter image description here

I couldn't figure out what I am doing wrong. Or is my last try correct way to do this? How can this circuit be simulated in SPICE so that we can see the common mode error is eliminated as claimed?

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    \$\begingroup\$ Removing the ground will leave an open node, which works sometimes but sometimes introduces numerical instability. Technically there is a fp cap on those nodes but best to also put some resistance on it. \$\endgroup\$
    – Voltage Spike ♦
    Apr 22, 2022 at 18:08
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    \$\begingroup\$ Does anything change if you use [Opamps]->UniversalOpamp2 instead of the LM324? \$\endgroup\$
    – Ste Kulov
    Apr 22, 2022 at 20:35
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    \$\begingroup\$ The opamp you're using for the DAC is nothing but a G+(R||C). \$\endgroup\$
    – a concerned citizen
    Apr 23, 2022 at 8:22
  • \$\begingroup\$ @SteKulov No it didn't make any difference. Im looking for someone to simulate what that paper claims. \$\endgroup\$
    – ty_1917
    Apr 23, 2022 at 19:33
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    \$\begingroup\$ This is an erroneous application of a common mode signal. Please describe the overall system you are simulating. From the description, it sounds like you have a voltage reference, DAC and differential transmitter system. 1. How would the reference be subject to common mode error? The reference is the most important signal in the circuit, why would it be exposed to a noise source? 2. There is one node only, Vref, not a difference; there is no common mode, this is normal mode, or single-ended; CM is meaningless here. 3. Would it not be more meaningful to simulate CM as a voltage offset... \$\endgroup\$
    – Tim Williams
    Nov 8, 2023 at 14:15

2 Answers 2

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I simulated this using LT1007A for all three opamps, using the voltage divider. I got 237uV P-P with the dividers grounded and 470uV P-P without them grounded.

My output is also centered on 0 V.

enter image description here

I suspect the problem may be in the opamp model you're using for your DAC model.

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  • \$\begingroup\$ You set R1 R2 and DAC resistors equal. But if you vary them you will see huge common mode voltage appear at the output. But in reality it shouldn't be the case. That should be independent of R1 and R2 and also DAC output. I doubt the models we tried is correct so far. \$\endgroup\$
    – ty_1917
    Apr 22, 2022 at 18:18
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    \$\begingroup\$ The whole point is to cancel out the common mode voltage by adding Vref in the inverting amplifier, if you change the voltage ratio of course you'll get high common mode voltage at the output. Without the second divider you get 1V + (-0.5V) = 0.5V, with it you get 0.5V + (-0.5V) = 0V. \$\endgroup\$
    – GodJihyo
    Apr 22, 2022 at 18:31
  • \$\begingroup\$ Yes but that means the model is wrong. R2 can be a poti to change the range of the output. And imagine even R1 and R2 is equal when the DAC will vary(means in my DAC model its resistors will vary). That means this model would be useless unless it outputs zero always. I need a model that can replicate the real scenario. \$\endgroup\$
    – ty_1917
    Apr 22, 2022 at 18:37
  • \$\begingroup\$ When the DAC varies the common mode should not vary that much. DAC model like mine can be wrong as well. \$\endgroup\$
    – ty_1917
    Apr 22, 2022 at 18:40
  • \$\begingroup\$ Shouldn't U3 source come from U1? \$\endgroup\$
    – Tony Stewart EE75
    Apr 22, 2022 at 18:56
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Your model will only be correct at DC operating points and low frequency AC. You have frequency-dependent elements that won't be common-mode rejected that shows up as a differential-mode signal at the inputs as U2.

What I would do, is omit U1 (it does nothing useful from the standpoint of simulation) and change U3 to an ideal op-amp. This will correct your simulation results.

Another issue that you may be having is common-mode signals on a DAC reference input will be seen as a differential mode signal on following stages - it's effectively the "gain" of the DAC and output will scale accordingly.

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