Please note that i1(t) is the loop current (in loop analysis method) and not the inductor current.
The answer to above problem is option B, which is derived below Following principles are used:
- Capacitor acts as an open circuit under DC steady state.
- Inductor acts as a short circuit under DC steady state.
- Capacitor volatge and inductor current cannot change instantaneously.
When I tried the simulation, it seems V(C1) (V(1,2) in the snap) is settling to input volatge and V(C2) (V(3) in the snap) remain as zero. I realize this is also a stable steady state solution.
My doubts are:
Looks like there are 2 stable solutions for this circuit.
V(C1) = input voltage, V(C2) =0
V(C1) =V(C2) = half of input voltage
What is the exact condition which determines which solution the circuit will eventually settle to?
In the simulation result, I see the capacitor voltage rising instantaneously. Not sure how is it possible. (Note: Initial voltage is set to zero). Looks like some simulation basics I am not aware of.