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I have to reuse an old VHDL draft design which was not fully verified and validated.

The code is huge - it takes around 30k slices to be implemented on an FPGA. I see that some signals are forgotten to be reset.

Is there a way to list all non-reset signals with a tool like Vivado or Quartus, or maybe a method?

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    \$\begingroup\$ Well, in the simulation you will get "Unknown" value for these before they are assigned. \$\endgroup\$
    – Eugene Sh.
    Commented Jul 6, 2022 at 14:51
  • \$\begingroup\$ I tried to review all them in simulation. Some of them are initialized, thus not undefined \$\endgroup\$
    – dsp_curious
    Commented Jul 6, 2022 at 15:00
  • \$\begingroup\$ You mean initialized as in initial block or some other non-synthesizable way? \$\endgroup\$
    – Eugene Sh.
    Commented Jul 6, 2022 at 15:01
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    \$\begingroup\$ There are tools like Questa Autocheck, but they are licensed for industrial use. If Verilog, you could have used open-source tools like Verilator Lint. \$\endgroup\$
    – Mitu Raj
    Commented Jul 7, 2022 at 4:52
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    \$\begingroup\$ You can consider writing a perl or python script which parses your VHDL file and find out the signals which are not reset. For eg: Filter out all signals which have been declared inside architecture, then filter out the signals which are not assigned inside if(reset) block. This would have been simpler job if all the clocked signals have a specific naming convention like 'xx_reg'. \$\endgroup\$
    – Mitu Raj
    Commented Jul 7, 2022 at 4:58

1 Answer 1

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I found a solution to list all forgotten resets of a design or module. This is possible with the tool called Synplify Pro.

The tool is not free in its standalone version I guess. But it is possible to use it in a free version through Lattice Diamond tool. Lattice Diamond tool uses Synplify Pro for synthesis. It is included in the install. The license is free (to download on Lattice website)

I created a project for my module with Lattice Diamond tool and opened the .srr file generated after synthesis and found the following warning:

@A: CL282 :"C:\test\test\vhdl\counter.vhd":40:4:40:5|Feedback mux created for signal busy. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.

This is a single line for one signal, there are much more in my srr file.

My resets are asynchronous ones.

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