Problem with reading a .csv file into a Verilog module

Question

I was trying to read a .csv file and use its contents. The csv is formatted as:

0001,1010,1110
0101,1100,1001

My code is:

`timescale 1 ns/10 ps  

module tb;
    
    reg a, b;
   
    reg[3:0] r1;
    reg[3:0] r2;
    reg[3:0] r3;

    integer i, f, j;

    initial
    begin 
        
        f = $fopen("vec.csv", "r");
        
        for (i = 0; i < 2; i = i +1)
        //while(! $feof(f))
        begin
        
            j = $fscanf(f,"%b %b %b",r1,r2,r3);
          
            #20;  
        end
        $display("%b,%b,%b", r1, r2, r3);

        $fclose(f);
        $display("pass");
    end
endmodule

The output is:

0001,xxxx,xxxx                                                                                                 
0001,xxxx,xxxx                                                                                                 
pass 

It seems that it can't read anything besides the first 4 bits of the 1st line. Could you tell me what I am doing wrong?

Answer 1

Try inserting commas ,

      j = $fscanf(f,"%b,%b,%b",r1,r2,r3);