Decoupling capacitor and ground fill

Question

I'm working on a 4-layer pcb project. Nothing is really high-speed on it (except for USB). I'm planning to have a ground plane on the top inner layer, and to ground fill the top layer.

In this case, is it good idea to connect the pins of decoupling capacitors of an IC (a STM32L4) directly to the ground fill? I'm afraid to catch some noise from the ground fill. The alternative would be to put a gap between these pads and the ground fill, and to connect directly decoupling capacitors to the inner ground plane with a via. Or maybe to create a local GND fill around the IC, which would be connected only to the inner ground plane with some vias.

I read some references about good grounding and EMC (EMC engineering from Henry W. Ott e.g.) but I didin't find any clear answer or argument to choose between these solutions.

Thanks!

Answer 1

Topside ground isn't very interesting, because it doesn't couple strongly to other shapes on the top side. That is, edge-wise coupling is low, ca. 10% at typical PCB fab minimum spacing. Whereas coupling for shapes over ground plane, particularly when it's a nearby inner plane, is much stronger.

Coupling can be measured in terms of effect on characteristic impedance of a transmission line. Compare microstrip (and 2 vs. 4 layer board), vs. coplanar waveguide with ground (CPWG). CPWG isn't much less, so it's enough that you might bother in certain priority applications, but for the most part it doesn't do anything.

As for bypass, you want to minimize the loop length/area to the bypassee. If top side ground helps you with that, great. More likely, just placing vias nearby gets you a shorter, lower, wider loop back to the pin(s).

Whether or not it helps with the local loop in question, I would guess two things are generally true:

1. Cutting pads from topside GND makes things worse: a longer loop to nearby GNDs, more trouble to lay out, more potential mistakes to make (did I remember to ground C47 too?..);
2. Direct pours to chip components sink a lot of heat from them. Which is great for power applications, but can be problematic for soldering, where the first pad to melt tends to suck up the component (tombstoning). Try to match the width of connecting copper; if one pad is connected by trace, maybe use only two thermal spokes instead of 4; avoid direct (fully poured around pad) connections.

So, #2 is a more subtle, inbetween case from what you were thinking; and with completely different motivation, as it turns out!

Answer 2

To evaluate where you can pick up noise you need to evaluate where current will flow on your board. If, for example, the via from your decoupling capacitor is positioned in such a way that power (or a signal return path) to a nearby sensitive chip passes current trough the same via you will pick up noise. Same thing with local grounds.

Decoupling capacitors shall have as low impedance as possible to the "stuff" they are decoupling. Decoupling capacitors are required because there is some inductance between the power-supply and IC. If you start adding gaps or local grounds you are probably making this inductance worse, decreasing the performance of the decoupling capacitor.