Why does this file give me "syntax error: I give up." in EDA Playground?

Question

This is my original file saved as "design.v"

module mef(
           input logic E, CLK, CLR,
           output Y);
  
  parameter [1:0] S0 = 2'b00;
  parameter [1:0] S1 = 2'b01;
  parameter [1:0] S2 = 2'b10;
  parameter [1:0] S3 = 2'b11;
  
  logic [1:0] atual_estado, proximo_estado;
  
  //Lógica de próximo estado
  always@(atual_estado or E);
    begin
      case(atual_estado)
        S0 : proximo_estado = E ? S0 : S1;
        S1 : proximo_estado = E ? S0 : S2;
        S2 : proximo_estado = E ? S0 : S3;
        S3 : proximo_estado = E ? S0 : S4;  
        S4 : proximo_estado = E ? S0 : S1;
        default proximo_estado = 0;
      endcase
    end
  //Atualização de registradores
  always@(posedge CLK)
    begin
      atual_estado <= 0 ? S0 : proximo_estado;
    end
  //Lógica de saída
  assign y = atual_estado == S3 ? 1 : 0;
endmodule

This is my testbench file saved as "testbench_tb.v"

module mef_tb();
  logic E,CLK,CLR,Y;
  
  mef inst1(E,CLK,CLR,Y);
  
  initial 
    begin
      $monitor("time = %g, E = %b, Y = %b", $time, E,Y);
      $dumpfile("mef.vcd");
      $dumpvars(0.inst1);
    end
  //Iniciando as variáveis em um valor conhecido        
  initial 
    begin
      E = 0;
      CLK = 0;
      CLR = 0;
    end 
  //Atualização do clock 
  always
    begin
      #1 CLK = ~CLK;
    end
  //Variações das entradas
  initial
    begin
      #2 CLR = 1;
      #2 E = 1;
    end
  
  //Tempo para finalizar a simulação
  initial
    begin
      #30 $finish;
     end
  
endmodule

Command I runned:

ICARUS VERILOG 0.10

Error reported:

design.sv:3: syntax error
I give up.
Exit code expected: 0, received: 1

Answer 1

The error message that the simulator gives you isn't very helpful because it is a tricky syntax error.

You mistakenly placed a semicolon at the end of this line:

always@(atual_estado or E);

Just remove the semicolon:

always@(atual_estado or E)

But, there are still more syntax errors. You tried using the S4 parameter, but you did not declare it. Since you have 5 states, you need to change your state variables to be 3 bits wide, not 2 bits wide. Something like this:

  parameter [2:0] S0 = 3'b000;
  parameter [2:0] S1 = 3'b001;
  parameter [2:0] S2 = 3'b010;
  parameter [2:0] S3 = 3'b011;
  parameter [2:0] S4 = 3'b100;
  
  logic [2:0] atual_estado, proximo_estado;

The last syntax error I see is on this line:

  $dumpvars(0.inst1);

I'm not sure what you are trying to do there, but you can simplify it as:

  $dumpvars;

This will dump all signals throughout the hierarchy, which is a reasonable thing to do for such a small code sample.

Those changes fix all the syntax errors.

---

For consistency, change:

    default proximo_estado = 0;

to:

    default proximo_estado = S0;