I am a student and new to digital logic simulations. Just curious as to why there is a very short response in OUT_02 at about 1.75 s.
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1\$\begingroup\$ Why? Because the logic circuit will produce that pulse. Can you justify why it shouldn't be there? I can't justify why it shouldn't be there --> is it intentionally there i.e. is it a wanted feature? Can you say why you believe it to be unwanted? \$\endgroup\$– Andy akaCommented Oct 7, 2022 at 9:37
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\$\begingroup\$ Perhaps to see it better, you should increase counter frequency. \$\endgroup\$– Antonio51Commented Oct 7, 2022 at 10:10
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\$\begingroup\$ As you're a strudent, Andy's comment is really very much better than my "logic" answer. Something about that short pulse it made you think it was strange and perhaps undesirable. What made you think that? \$\endgroup\$– jonathanjoCommented Oct 7, 2022 at 10:32
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1 Answer
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You noticed something important and you should follow it up to find out what exactly is causing it.
It looks like there is a race condition in the logic, such as the term in_03 xor out_01 appearing somewhere, and at t = 1.75 s one of them changes fractionally before the other. Short, but not so short that your simulation misses it.
In fact, it is very possible there are glitches at t = 0.25 s and t = 2.25 s, but the resolution of your simulation doesn't show them.
answered Oct 7, 2022 at 6:53