Why does this circuit's output oscillate/behave erratically?

Question

I built the following pulse-width-recognition/digital-filter circuit on a solderless breadboard. I used 1/4 of a CD4011BE with another 1 µF bypass capacitor as the inverter, a perfboarded CD4060 circuit that has been verified to work as the 512 Hz clock source (CLK), and my AFG-2012 as the 2.5 Hz/90% duty input signal source (SIG):

^{simulate this circuit – Schematic created using CircuitLab}

Instead of getting a "clean" output from the circuit of any sort, I get erratic output from the counter instead (channel numbers are as shown in the schematic, ignore the labels I have set on the scope):

Is this a sign that I accidentally fried my counter chip and should replace it (with better attention to ESD precautions and so on), or is my concept of operations, namely that the counter "freezes" itself at 0 after counting down until the input signal goes low again, hopeless to begin with?

Update: I tried putting a new counter chip on my breadboard, taking proper ESD precautions in the process, and the circuit's behavior did not change. Can someone explain to me why the circuit I have is behaving the way it is?

Update 2: with the replacement counter chip installed, I tried taking a pair of new scope shots, one of the overall behavior and one zoomed in on the rising edge of the output, both with the clock as CH3 instead of the original use of it to directly monitor the counter's output.

Update again: was able to get a full-sample-rate zoomed in shot (and fixed the coupling issue on CH3):

Another update: I got a shot at 250MSa/s + 6MPts with the timebase at 50ns/div when the capture was taken, using an inter-channel delay trigger to set the trigger edge where I wanted it:

Answer 1

What appears to be happening is the CD40103 counts down from 255 to 0 (which takes ~40 ms) causing CO/ZD to go low ~90 ns after the clock rising edge, as expected. However this is then fed through the inverter to CI/CE, causing it to go high ~30 ns later which then makes CI/CE go low again. This cycle repeats a random number of times until the counter resets and counts down from 255 again.

The operation of control inputs to the CD40103 is quite complex, and the timing diagram only shows a few of the possible combinations. According to the datasheet counting is inhibited when CI/CE is high. However if all inputs except CI/CE are high at the time of zero count (CO/ZD low), the counter is reset to maximum count and counting is enabled.

I suspect that disabling and then re-enabling CI/CE so soon after clocking causes a race condition where the counter doesn't get properly reset and just toggles CO/ZD and CI/CE alternately for while, until eventually it does reset and counts down normally.

I'm not sure what you are trying to do with this circuit. If you want the count to stop at zero until SIG goes low then perhaps what you need is a bistable latch that is set by CO/ZD going low and reset by SIG going low. This can be made with 2 NAND gates in place of the inverter. You may still have trouble if SIG changes state at the same time as CLK, in which case you could feed SIG through a D flip-flop to synchronize it.