I'm trying to build a modulus 11 counter that will count from 0 to 10 and reset at state 11 in Multisim using a 4516 counter and a D-FF based off the following figure:
Because the D-FF inserts a delay of one clock cycle before the RESET signal is sent to the 4516 and the AND gate, I've place the 1 at 12 instead of 11.
Based on this I've set up my circuit in Multisim as follows:
However, It's not working correctly and counts up to 13 before resetting instead of from 0 to 10.
As ErikR observed, you haven't defined P0 through P3. However, assertions of PL on pin 1 of U1 are intended to copy the inputs from those pins to the counter's output.
In truth, you don't mean to use this feature at all. I can see this because you are using a decoder to recognize the pattern 11xx and through some additional logic you use that pattern to assert MR on pin 9 of U1. This forces the counter to take on the value 0000.
To avoid the conflict, tie pin 1 of U1 low and don't use the preset feature. I make a practice of not letting the inputs of CMOS integrated circuits float, so if you wish to follow the same practice, you could tie P0 through P3 low. With PL (pin 1) low, these will have no effect.
But there is another mistake. Consider the moment when the counter contains the value 1011 (11 in decimal) and the clock input CP on pin 15 of U1 goes high. This causes the counter to increment to 1100 (12 in decimal). The same clock pulse also is used to update the flip-flop in U2A. It will load a 0 because when the clock goes high, the 10xx pattern produces a zero input at D1 (pin 5) of U2A. I'm sure you were expecting it to recognize the pattern 11xx at this moment, but you must reckon with the delay of the signal through the counter. Effectively, the flip-flop is one cycle behind the counter. But even if you changed the decoding to recognize 1x11, you still would have an error because the output of U5A wouldn't go high for another half cycle, since U4A makes U5A run on negative-going clock edges. This would cause a reset halfway through the display of 1100. But since you're not decoding 1x11, but 11xx, the counter outputs 1100, then after one cycle the D flip-flop recognizes this, but at this moment the counter outputs 1101. After half a cycle, the D flip-flop's output causes a reset of the counter halfway through the pattern 1101. That's why your counter goes to 13 no matter what you do with the preset pins.
Because the counter does not have a synchronous-load feature, you can't make it hold the pattern 1011 for a full clock cycle, and then output 0000 except by asserting the reset at the MR input (pin 9). It's an asynchronous input, so takes effect at once, but the counter will have fleetingly counted up to 1100 before the decoding logic can take effect and cause the MR pin to go high. If you don't mind the brief appearance of 1100, just change the decoder to look for 1x11 and get rid of U4A. This will cause the counter to go very briefly to 1100 and then reset to 0000 when the clock goes high. You will never see it on the lights, but if you're using the counter's output to do something, other circuitry might observer and act on that brief 1100 showing up.
If you use a different counter, one that allows synchronous loading of a desired pattern, then you can avoid the brief appearance of the objectionable 1100 output altogether.
