Best layout practices for high-impedance PCB design

Question

I have built three very high input impedance amplifiers; under 1 pF, over 100 MΩ.

---

One some else's design and layout, very high input impedance, but low frequency; several MHz. Not shown below.

---

The second one I layed out hoping frequency response to 30 MHz, but it dropped off of 17 MHz. Probably poor layout.

---

For the next one I received advice to skip the SMD and use through-hole (seems counter intuitive).

It is a different schematic and is supposed to reach 90 MHz, it did pretty well, but had a level bump at 29 MHz, I had etched away the underside ground plane, I covered it with a grounded copper tape and that removed the level bump and it is pretty flat to 30 MHz, well under 1 dB.

---

Now I want smaller, so I'm going through the learning curve of learning KiCad to design an SMD high input impedance PCB.

Any hints on how to limit the strays that cause problems?

Answer 1

Maybe you can play with the circuit in simulation with various parasitic capacitances added. The effects are reduced by maybe 5:1 (but not eliminated) by the bootstrapping.

You could consider using a string of resistors for the gate bias resistor, for example.

Extending bootstrapped copper under (or around but not under) the resistor body and input conductor may also be effective. That connector must contribute significantly.

Using through-hole components for the JFET and input bias resistor may be helpful because you can get them off the PCB (with its high K \$\approx\$ 4) and into the air (with K = 1).

At 30MHz, 1pF of capacitance has impedance of around 5kΩ, so the impedances are not really particularly low, rather the effective input capacitance is low.