I was reading the datasheet for the voltage regulator uA7812 to implement in my circuit and it says at page 15:
Keep trace widths large enough to eliminate problematic I×R voltage drops at the input and output terminals. Input decoupling capacitors should be as close to the μA78XX as possible.
Why should the decoupling capacitors should be as close as possible to the voltage regulator? What does it mean by "trace widths"?
Input decoupling caps are there, among other things, to provide an easily-accessible source of charge/current for the device they're attached to. Since capacitors are able to discharge on very short timescales, they are well suited for minimizing voltage dips when the powered device suddenly needs more current (turning on outputs or loads, for example). Positioning them close to the power input pins minimizes the resistance and, more importantly, the inductance of the path the current must take from the capacitor into the device since inductance will oppose the extra current coming from the capacitor. Making the wiring or circuit board traces connecting them as wide as practicable also reduces the resistance in this path.
In this example, C1 is connected to U1 with short, wide traces while C2 is placed (relatively) far away from U2 and connected with thin traces. In a real project you will have other components and layout considerations to juggle, but this is what the datasheet is talking about.
There is a relevant length scale here, which isn't evident from the datasheet. Mainly because they say "minimal is best" and leave it at that, but one would like to know: minimal compared to what? When does it really matter?
The answer depends on cutoff frequency and required impedance. 78xx for instance have cutoff in the 100s kHz to low MHz, with impedance in the several-ohms range, so "minimal length" can be some inches and it won't really matter to it. Regulators with lower impedances and higher cutoffs will be more demanding, perhaps needing under an inch.
The same applies to bypassing of anything. CD4000 logic for example hardly needs anything at all (maybe within a foot?). 74HC generally needs it within some inches. 74LVC and other fast families (also including many MCUs, ASICs, etc. that are built on a similar process node), some cm, or mm even.
You also want to avoid inductive links between low-ESR capacitors, which can introduce resonant peaks to the power distribution network (PDN).
The PDN can be modeled by taking trace (and component body, pin, and via) lengths together as inductance, L ≈ 1 nH per mm of length. Series R-L-C models will suffice for capacitors (if ESL isn't given, assume a value based on lead and body length). You want to dampen or terminate LCLC.. networks with lossy "bulk" capacitors (usually electrolytic or tantalum type, but polymer are also available with modest ESR, or ceramic can be used with an external resistor). I won't go into network theory here, but this can all be modeled in a fairly straightforward way, to first-order accuracy, which is usually good enough to see the major peaks and troughs in the response.
