What is the role of master clock speed on DAC?

Question

In the I2S protocol we have 3 signal + one none-standard master clock (mentioned by Olin Lathrop):

1. data
2. LRCK/FCK (frame synchronizer)
3. BCK (bit clock)
4. MCK/SCK (master clock)

Question 1: Why do we need a master clock? I think some devices simply need a clock to work; this master clock can provide the clock for them to work.

Question 2: In the PCM5102a DAC IC we have specifications about the relation of the master clock (SCK) to the sampling frequency (LRCK):

But what is the difference between these multipliers? In other words, by providing a higher or lower frequency clock for the DAC, what will change, what will happen? And how can we choose one of them? I can't find anything about it in its datasheet.

Question 3: As you can see in the picture from the datasheet appended above, without providing SCK, it will use its own PLL to generate a clock for itself, but according to the picture we have two speeds supported, 128x and 192x. Which one will be selected how? Again, I couldn't find anything in the datasheet.

Question 4: Also the datasheet mentioned 1x/2x/4x/8x interpolatino is availible, but there isn't way to setting it, does it relate to MCK?How?

Answer 1

The PCM510xA system clock detection circuit automatically senses the system-clock frequency.

The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically.

In other words, there's nothing for you to do, except supply a clock at any rate that appears in the table row for your sample rate, and the chip will detect which one you're using and automatically divide it down. The allowed values are all of the powers of two between 128x the sample rate and 50MHz (except for 384kHz sample rate, which is special and allows a 64x SCK).

Question 3: As you can see in the picture from the datasheet appended above, without providing SCK, it will use its own PLL to generate a clock for itself, but according to the picture we have two speeds supported, 128x and 192x.

What really matters is Table 11, which shows two things:

1. The BCK has to be between 32 and 64 times the sample rate, depending on your bit depth (also shown in Table 2).

2. The BCK has to be above 1 MHz for the PLL to lock; low sample-rate/bit-depth combinations that would result in BCK below 1 MHz are forbidden in the PLL mode.

The (2) annotations in Table 10 are just showing the values of SCK that can come out of the PLL for various values of BCK. This is probably not important to you. We can guess that the PLL doesn't divide by 3, therefore the "128x" values result from 32x and 64x BCK, while the "192x" values result from 48x BCK.