Why isn't my current mirror reflecting 500uA on each side?

Question

I'm designing a telescopic cascode with a tail current source of 1mA. I had set my VDD to be 2V and all of the mosfets in the schematic seem to be saturated but the current reflected by the current mirror in the top left of the schematic only gives 240uA on each side when it should be giving 500 uA. The difference could be because of channel length modulation so would I then have to increase the lengths of M1 and M4 as well as M8 while keeping the aspect ratios of each the same? Below are images of my schematic showing the component parameters of each of the transistors as well as the DC operating points. Also it's a little bit hard to see but right next to each voltage source is a number in white text showing its voltage. If anything's difficult to read or if you have any questions, please let me know.

Answer 1

You've run out of headroom. Note M1's operating point:

Vds is significantly smaller than Vgs in magnitude, suggesting that the transistor has entered triode, its small signal output impedance has dropped, and it is no longer a good constant current source.

While it's hard to tell for sure without having your PDK and replicating the whole circuit, my suspicion is that the gate voltage of M0/M3 is too high; in proper biasing, this transistor's Vgs is set based on its current, and hence its source voltage (i.e. the drain of the current mirror) is one Vgs drop higher than the gate voltage you chose. Also, note that a lot of your headroom is used up by M20/M22, which have a Vds of over 1 volt.

Rather than setting the bias voltages V7 and V8 manually, you may want to consider a replica biasing approach. If you still can't get enough headroom, consider a folded cascode rather than a telescopic cascode. This has other upsides, including the fact that you don't have to choose the same current for the input and output branches, but also some cost of complexity.

While I'm looking at this circuit, a few other notes:

• Unless you have isolated wells or an SOI process, your body terminals may need to go to the corresponding rail (VDD for pFET, VSS for nFET) rather than be bonded to their source.
• A current mirror with different sizes for input and output FETs might be overly sensitive to PVT and hard to lay out in a neat manner. If you can size the mirror to use the same size transistor, and more or less parallel replicas on each branch, it may be significantly easier to get a well-matched and symmetric layout.