First, I just want to emphasize something peculiar about the context here.
This is apparently a safety driven design, perhaps even a life-critical aerospace or medical application. We [readers and answerers] can safely assume that some kind of large price will be paid by failing these conditions. Maybe it won't meet with immediate consequences (say, the safety features were bypassed but the system continues to function as expected), but eventually consequences will come (system fails to function, then safety features fail to report this change accurately).
And "large" might merely be a matter of equipment or infrastructure costs (borne by the end customer, or your employer, or their insurance, as the case may be), or it may be multiple human lives. Which is still a cost -- even in the most bleak, realist, psychopathic economic terms, lives correspond to some millions of dollars each; depending on where they're located, of course.
Contrast this with where we are: the internet. Anyone, anywhere, relatively anonymously, can join and submit an answer here.
That's not to say you can't get good answers from the internet. And you might get poor answers, and they might be downvoted, it's true, there is such an identification mechanism here. But there's also a massive gulf between answers that look good enough to pass casual inspection and which aren't worth downvoting; and well-informed, responsible and accountable answers. Indeed, the latter tend not to be upvoted as much, simply because they are more difficult to assess.
So, beyond the most obvious cases, you are left with nothing but your own critical faculties to assess whether an answer is reasonable or not.
And, not to cast aspersions or anything, this is just my assumption, or opinion -- but given the discrepancy between the above facts, one would be right to question whether those faculties are adequate, given the weight of the task at hand.
As a result, I strongly urge you or your employer to see out a professional consultant skilled in the matter. A consultant (or employee, or whatever) won't be cheap, no. But they also won't cost lives, or future materials costs or lawsuits or insurance premiums.
Anyway, given the above; as another random agent of the internet, let me do my duty and offer dubious information, suitably steeped in varying amounts of helpfulness, over-seriousness, and sarcasm, that you may use at your own risk.
We can approach the basic problem ("shortage of pins on the CPU card", if I'm not mistaken) in several ways.
If the signals are digital in nature (i.e. binary or other discrete levels), multiple can be assigned to a given pin (or pin pair, if everything is differential, as seems to be implied) by weighting them orthogonally. That is, say we have a termination resistor at the CPU card, and each peripheral card sources a current proportion to its state, times a factor related to its position or type. The resulting bus voltage is the sum of currents times the resistance: \$V = R \sum_i I_i = R \sum_i x_i c_i\$, where \$x\$ is the state variable (e.g., 0 or 1) and \$c\$ is the position current factor (e.g. \$2^n\$ times a reference current, for each \$n\$th card). This is simply the definition of positional numbers, and for the binary case, it reduces to a binary DAC. The base can be anything, of course, and it can even vary from card to card, as long as no combinations of codes are redundant (different states producing the same voltage). You may also want to error out on any "impossible" codes (gaps that are [should be] unreachable based on all possible states and the given weights).
Whether your CPU is able (mechanically speaking, or per the standard) to read this signal without state (such as a SAR or S-D ADC uses), or in the presence of interference / noise, is a separate issue.
If the signals are continuous in nature, and cannot be quantized to a digital value (or, to a reasonably small number of bits), they can be multiplexed in various ways.
TDM (Time Division Multiplex) generates a sequence of timing pulses, and during the respective time slot, each respective card gates its signal onto a common bus. The CPU then reads each slot accordingly.
This is a symbol*-serial communication mode, which, like any other serial mechanism, requires storing states. We can use a fairly simple cheat here: using a sample-and-hold module, store the analog voltage from each respective symbol on a capacitor. The values can then be read out continuously and in parallel. The downside is the stored value decays over time, so it needs to be read out within some time frame depending on acceptable error.
They can also be frequency division multiplexed (FDM). Each signal is modulated onto a carrier signal, and multiple carriers are summed onto the bus. The CPU card then separates each signal by filtering, and uses a detector to recover the original signal. AM is the simplest mode, and indeed this was the method used for early telephone trunking. This is simultaneously a simple and complex method; simple to implement in concept (few transistors are strictly needed), but complex to implement reliably i.e. at low distortion with good isolation between channels (in particular, the filters can be quite precise, depending on how densely packed you need the channels to be). Digital radio methods can of course offer greater density (higher performance for fewer parts), but again may not be applicable here.
There are other methods as well (e.g. orthogonal codes (CDMA)), but they are more complex so I will not go into them here.
*A symbol is a fixed level on the line, for some period of time. At least, it is for a typical time-quantized communication medium. On a digital serial port, a symbol is binary 0/1, and the period is the bit time (1/baud). The signals could be multi-nary: for example, 100BASE-T Ethernet uses ternary; many long-haul and radio modulations use phase-amplitude constellations containing thousands of states (i.e. >10 bits) per symbol.
No[,] analog states are not prohibited [sic]
Then digital states are allowed.
We can apparently solve this issue by using a capacitor to store state, for example.
Suppose we charge a capacitor to some voltage. That voltage will decay over time (the same issue with the sample-and-hold mechanism above). Suppose we only need to know approximately one bit of information about this voltage.
Note that analog signals are continuously variable, but might not be very "informative", or might be noisy enough that not much information can be obtained from it. We can express this as an equivalent number of bits (ENOB), or entropy, or other measures. These are continuous measures -- ENOB needn't imply a fixed number of bits, but can be fractional as well. In this sense, we can have a variable amount of information known about the signal.
Note our input isn't digital, it's continuously variable and contains a potentially variable amount of information; we're just "crushing" it down to one bit of output, and making the assumption that this is all we need to know about the input.
simulate this circuit – Schematic created using CircuitLab
To perform that "crushing", suppose we apply a negative resistance to the capacitor, and add clamp diodes so the voltage remains constrained between limits. (In practice, the negative resistance element has finite range already, but we can model it this way.) Now any voltage different from zero, will be amplified by the negative resistance, pushed towards the limits, and clamped by the respective diode. Any subsequent time we measure the capacitor, we find its voltage is as it was left, somewhere above or below zero; or after enough time, approaching or at the clamp voltage.
In this process, I have not specifically invoked an element of digital logic (a flip-flop), which would seem to be supported by the spirit of the standard as related here. But notice its output is fully digital: it has two stable well-defined output voltages, corresponding to an input within some bounded range (for input-high or input-low respectively). Have we therefore, in fact, constructed a digital memory? But how can that be, it is a continuous differential system (that is, we can express its behavior with a differential equation over continuous variables)!
Similarly, we can use analog states to construct counters, adders, etc. Analog computing is of course Turing-complete, assuming some means of expressing the expandable or unlimited memory requirement of a true Turing machine, of course.
For example, we can construct a counter using a current source into a capacitor: the voltage rises linearly with time. To get a digital sequence output, for example, simply use an array of comparators, and (combinatorial*) logic to resolve their outputs into windowed ranges; or a binary sequence, or whatever we like. (We can also use the same method (comparators and logic) to translate an analog signal into a binary representation while using no internal state: this is known as a "flash" ADC.)
Indeed, note that we can construct a SAR ADC this way, by storing acquired bits into a register S&H array, subtracting the difference (from the latest acquired bit value) from the input then doubling its scale (the input S&H capacitor's voltage is latched in recurrently from this subtract-and-scale function), and we've apparently never used "digital memory" in the process.
*Combinatorial logic (free of feedback loops) is stateless, so would seem acceptable here.
Perhaps we can even construct an SPI or I2C interface in this way!
But indeed, perhaps you are starting to see the problem here. There is a fundamental category error. Digital is not beside analog, it is a strict subset of analog. Indeed, no stipulation of the capacitor value, or the negative-resistance mechanism, is required of the above description of a "one bit" S&H, and digital logic solves this by using minimal capacitance (parasitic amounts) and pairs of transistors (as in SRAM and other flip-flops). So I've described sequential digital logic without having called it as such until here.
Whether this error is due to an incomplete description of the standard, or the standard itself is ill-conceived, I don't know.
It certainly isn't possible they mean to remove any state, as that's fundamentally impossible to a certain extent (EM fields around wires are indeed state, albeit very transiently so -- perhaps nanoseconds scale, unless carefully "gamed" to much longer time scales -- as in practical capacitor and inductor components), and a restriction on the amount of filtering for signal lines (filters are [analog] stateful!) would surely be counter to the root purpose of reliability.
It also seems unlikely that they would intentionally seek to prevent one of the most reliable tools available to engineers today: digital logic, used responsibly, offers truly minuscule bit error rates. A modern CPU, just by sheer nature of existence, without any special error-correcting functions (software asserts, error-correcting memory, redundant CPUs, etc.), incurs parts-per-trillion error rates! Now, while I would not stake my life on such a system (mainly because, not only is it performing billions of such calculations per second, but because the software that runs on it is incomprehensibly complex and not made to anywhere near the same standard as we're talking here), I would be more than confident using the few bits of digital logic that seems to be requested here.
It seems likely to me that a more nuanced description of the standard exists, which simply asks you not to abuse stored states on signals that must be read regularly, or indeed continuously (up to whatever their respective bandwidths are), so as to avoid data-redundancy and coherency errors (that is, the value read in one place, is supposed to equal the value in another place, but in fact differs because of some failure of the update mechanism). Whether this materially limits your implementation as far as the number of cards supported on the limited-pin-count backplane (and so your question is, by strict application of the standard, impossible), or whether some multiplex method is permissible, is not possible to determine here.
