IIM-42352 interrupt triggers multiple times, when condition is only met once

Question

Currently I am working with esp32-s3-mini system which communicates with IIM-42352 accelerometer via SPI. My configurations are as follows:

*FIFO mode- stream to FIFO

*Packet size- 16 bytes

*Interrupt 1 triggers when FIFO element count passes watermark value.

*Interrupt 1 is in pulse mode and only routed to Watermark threshold condition.

I want to fill buffer half way, get an interrupt, then start reading whole buffer, while I am reading the buffer, it should continue to fill up and when it reaches end, it should start filling from the beginning, this way I should avoid loosing data. For starters I tried configuring buffer so it would work in FIFO to stream mode and put out high on INT1 when FIFO fills up to 112 samples. the problem I get is that interrupt is being triggered very often and on several conditions, even though I only sourced it to be held high on Watermark threshold. After reading Int1_Status reg I get these bits 00001100, which means that FIFO buffer passed threshold value (which is good) and some kind of Data ready interrupt is triggered:

I do not really know what this Data ready even does, because I do not use it and can't find any info on datasheet too. And if this Data_Rdy_Int is not triggering interrupt, what might? Watermark threshold should trigger INT1 interrupt once, after FIFO element count passes the Watermark value, if I am not reading the buffer, element count should always stay at full, only new data is over writing old one. What could cause these multiple interrupts? And what does Data ready mean? https://invensense.tdk.com/wp-content/uploads/2021/01/DS-000442-IIM-42352-TYP_v1.4.pdf

Answer 1

DATA_RDY_INT is the interrupt signal if you are reading directly from the accel/temp registers and not the FIFO. It triggers whenever there is a new sample i.e. it goes at the output data rate (ODR).

Have you looked at 14.45 of the V1.4 datasheet and cleared bit 3 of INT_SOURCE0?

And do you have the right pulse duration set for your ODR? That's also controlled by INT_CONFIG1.

Also look at 14.44 and clear bit 4 of INT_CONFIG1 for 'proper INT1 and INT2 pin operation' whatever that means.

Note: for future readers that come across this and want to use DATA_RDY_INT with the latched interrupt you'll want to look at INT_CONFIG0 in section 14.43. I cleared bits 5:4 and then had to manually read INT_STATUS once to trigger the first interrupt.