GENERATE statements in VHDL

Question

I am investigating using GENERATE statements in VHDL to make duplicating the same logic tidier and more efficient. Take a basic example I found online below:

type array_of_100_unsigned is array 0 to 99 of unsigned ( 7 downto 0 ) ;

signal x , y , result : array_of_100_unsigned ;

generate_100_adders : for index in 0 to 99 -- The following compact code will generate 100 adders.

generate

single_adder : adder

port map
(
  input_a => x ( index )  ,
  input_b => y ( index )  ,

  output_c => result ( index )
) ;

 end generate ;

This code produces 100 adders instead of having to write 100 lines of code in theory. So when this code is synthesized there will be 100 instances of this logic implemented in hardware and cannot be changed.

Can this be made more dynamically configurable? I.e. could we add logic that could change the number of adders in run time after synthesis when the design is running on an FPGA? Or is this logic fixed once mapping the bitstream on chip?

In the same example below, could we use a variable instead of hard-coding the 99 here?

generate_100_adders : for index in 0 to 99 -- The following compact code will generate 100 adders.

Answer 1

VHDL describes the hardware you generate. It does not contain any inherent mechanisms to change the hardware after synthesis, in a matter analogous to self-modifying code. Whatever hardware the synthesizer generates will be unchanged thereafter.

It's possible to provide additional hardware to determine how many adders are used on the fly, but the full complement will always exist until the design is resynthesized.

It's also possible that the synthesizer will optimize out some of the instantiated blocks, for instance if their outputs are unused in the design. However, once the synthesis is complete, the hardware is fixed.

A further possibility is that some technology offers the ability to modify hardware on the fly, but this is independent of VHDL.