In verilog, what effect does the not (!) operator have on high impedance and don't care conditions?

Question

I'm writing some verilog and simulating it using modelsim. I have a block that looks like this:

        if(wr_req & !cam_busy & !lookup_latched & !cam_match_found & !cam_match_found_d1) begin
           cam_we           <= 1;
           cam_wr_addr      <= wr_addr;
           cam_din          <= wr_cmp_data ;
           cam_data_mask    <= wr_cmp_dmask;
           wr_ack           <= 1;
           lut_wr_data      <= wr_data;
        end

lookup_latched is in high impedence. cam_match_found and cam_match_found_d1 are both in don't care states.

It seems to me like the statement should just ignore those signals.

The one issue I noticed was that the signals were being bitwise anded instead of logically anded (I didn't write the code). Will this have an affect on the result? (I imagine it will)

Thanks!

Answer 1

Your code will not work.

In verilog, a 'z' at the input of a gate transforms to an 'x' on the output of the gate. An 'x' at the input of the gate also translates to an 'x' on the output of the gate.

Therefore your code reduces to if(wr_req & !cam_busy & X & X & X)

The value of (something & X) can be either 0, or X, and in both cases the if statement will evaluate to false (if(X) is the same as if(0)).

The one issue I noticed was that the signals were being bitwise anded instead of logically anded (I didn't write the code). Will this have an affect on the result? (I imagine it will)

If those are all 1-bit signals, than logical AND (&&) is the same result as bitwise AND (&).