I was trying to build a normal class A amplifier, but no matter how hard I try, I cannot find the reason behind my output (blue line) being clipped at the negative cycle of the input (yellow line.)
What am I doing wrong?
This is the circuit:
This is the output:
You are forcibly feeding AC from AC source that is directly connected into transitor base, bypassing the DC bias resistors.
OP has neglected the input coupling capacitor (not shown in their schematic; let's tentatively call it C1). So it would be good to clarify what its role is here. There are several textbook approaches to this, the worst being that "the capacitor had a high resistance for DC and a small resistance for AC", that "the capacitor did not pass DC but AC", and that "the capacitor galvanically isolated the input source from the bias circuit". They are generally correct but do not explain exactly what is going on in the input circuit. A good intuitive explanation is needed for capacitor behavior in the time domain rather than the frequency domain.
The input capacitor can be thought of as a "rechargeable battery" which is kept charged up to the bias voltage and its voltage is added to the input voltage in series (according to KVL). Thus two voltage sources, one (Vin + Vc) perfect and the other (Vcc-R1-R2) imperfect, are connected in parallel so the former overrides the latter. Their DC voltages are the same so the input AC voltage is superimposed on them and appears at the output.
Bias circuit: Let's assume that the next transistor stage (represented by the voltmeter Vout) requires a 5 V bias voltage. We can get it from Vcc through a voltage divider R1-R2. Since the idea here is that the input voltage can directly change (in parallel) the divider's output voltage, the voltage divider must have a relatively high output resistance. Figuratively speaking, this is an "intentionally degraded voltage source" (with an artificially increased output resistance).
simulate this circuit – Schematic created using CircuitLab
Connecting equivalent voltage source in parallel: What will happen if we connect a perfect voltage source with the same voltage (5 V) in parallel to the output of the voltage divider? Nothing... Because there is no voltage difference, no current flows and the output voltage does not change (by the way, this arrangement is known as "bootstrapping"). The interesting thing about this "DC current-blocking technique" is that it does it through a reverse equivalent voltage and not through an infinitely high resistance (open circuit).
Inserting an input voltage source in series: Nothing changes even if we insert an input voltage source Vin initially with zero voltage.
Vin > 0: Let's now "wiggle" Vin; for example, first increase it with 1 V. Since the two voltage sources (Vin and Vc) are connected in series, in the same direction, their voltages are summed and the total voltage (6 V) appears at the divider's output. Note that this composite voltage source Vin+Vc injects current through R2 that is added to the initial divider's current. Figuratively speaking, the composite input voltage source "pulls up" the divider's output.
Vin < 0: Let's now decrease Vin with 1 V. As a result, the divider's output voltage becomes 4 V. Now the composite voltage source Vin+Vc "sucks" current from R1 that is subtracted from the initial divider's current. Figuratively speaking, the composite input voltage source "pulls down" the divider's output.
Of course, we can use the CircuitLab DC sweep simulation to see the process through time. As you can see, the input voltage is "lifted" with 5 V and appears at the output.
AC input voltage: So, in this way we can "move" (bias) the zero level of the AC input voltage from the ground to the divider's output.
Replacing the "battery" with capacitor: Now it remains only to replace the battery with the more convenient capacitor C. Even more interesting thing than above is that the capacitor blocks the DC current both through an open circuit (insulator) and a reverse equivalent voltage.
The operation of the circuit is exactly the same.
... is the absence of a "voltage shifting" element (charged capacitor) between the input voltage source and the divider's output. As a result, the input voltage appears directly at the output without being "shifted".
You can see the continuation of this story about the output coupling capacitor C2 in my next answer.
The original schematic, the oscilloscope trace or the words have been edited. Now the there is an input coupling capacitor, the base is at 10V and the emitter current is so high in the 2k emitter resistor that the resulting 4.65mA in the 20k collector resistor causes the transistor to be saturated.
If I read the "scope" right, that's 1 mV peak for input, offset unknown due to coupling "AC".
If I read the schematic right, the no input operating point has the emitter close to 1.8 V, same if the source was AC coupled or offset to about 2.4 V, and Q1 pretty much saturated:
What do you expect?
