My text book says in saturation mode, the base-emitter and collector-base junctions of BJT are forward biased and in cut-off mode both junctions are reverse biased.
But in this graph the saturation region represents \$V_{CE} < V_{\text{knee}}\$ while \$I_B = 0\$ is denoted as the cut-off.
Can someone please explain?
The diagram in your question, together with countless others like it, is incorrect insofar as it labels the shaded region on the left hand side, a region that the transistor CANNOT operate in, as the saturation region. It is a persistent error, but an error nonetheless. The edge of the shaded region on the left hand side is in the saturation region, but the interior of that shaded region does not correspond to any realizable operating state.
That being said, there is no "official" definition of saturation. Some may define it as your TA did, in terms of the base-collector junction being forward biased. Others may define it as when the current gain falls off by a certain amount, and so on. Understand what the user of the term means. Understand that a different user may mean something slightly different.
"Both junctions forward biased" is a simple, effective definition, but not really a complete, or realistic, one.
A practical definition (you'll find it in datasheets) is forcing hFE to a given value, a fraction of the active-region hFE. Note that hFE drops arbitrarily in the indicated region (the IB curves all pile up on each other), so we can simply supply excess IB, and let the collector pull down as far as it can (and, assuming a load line such as indicated, saturation will indeed occur).
You could perhaps reconcile the two cases by assuming some stray internal collector resistance, and probably emitter and base resistance too, which together affect VBE(on) and VCE(sat). That is, at the junction itself, both sides become forward-biased, but the terminal voltage is higher due to these resistances. I don't know quite enough about modeling or physics of real devices, to know if this is indeed a physical model; high voltage transistors in particular can have saturation voltages of several volts, far above VBE (though there could be still other reasons they're rated that way, but still have good and low saturation voltage in the average case).
As for IB = 0, it's "not forward", which I guess is good enough for them? Same provisions apply, I suppose.
In general, and especially at high VCE, there is some leakage current that flows C-B, which forward-biases the B-E junction, hence the IB = 0 curve sits above zero, but not just by ICBO but approximately hFE times higher; in this condition, we do indeed measure some positive VBE, and the transistor could be said to still be turned on, by its own behavior without having supplied external current at all. We could modify the condition to say IBE = 0 (leaving a mystery of what base pin current should be), or VBE = 0 (shunting C-B leakage, and setting the B-E junction "off" by definition), and the latter is a practical solution (a common sight is a B-E resistor to shunt this current, which gives faster turn-off switching as well).
Mind, for where you're at in the textbook, it may simply be these are sufficient definitions, and may be improved upon later.
This is a dirty trick, I think, but it is one often played on students, for better or worse; namely, giving partial or temporary definitions and not acknowledging them as such.
Consider what you thought you knew about square roots (probably): at first they say you can't take the root of a negative number; later you learn you can, it's just the result is in a different number system (\$\mathbb{C}\$) and they just didn't want to get into that yet. Or even hint that there might be anything at all to follow down that path.
Examining a pnp BJT, it can be stated that the possible polarizations are those depicted here. In the first, the BJT works in the linear region or even in interdiction. In the second it is in saturation. (The drawings were drawn by me with PAINT).
The graph you gave us is quite difficult to interpret in terms of reverse or forward bias states of the junctions, because it doesn't show collector, base and emitter potentials with respect to each other. You have to infer such information. I explain this in detail in another answer here.
To confuse even further, there are subtle hints in the graph you show us that a collector resistor is present in the test setup. Statements like \$I_C=\frac{V_{CC}}{R_L}\$, and \$V_{CE}=V_{CC}\$, in my opinion only serve to confuse. They might be true, but the context is misleading. Again I refer you to my other answer.
It's impossible to show the cut-off region in that graph to a realistic scale. If you look at that red-shaded cut-off region, it seems to indicate that collector current \$I_C\$ will be about 7mA in cut-off.
That's not realistic (except for certain specialised BJTs), because in cut-off, collector current is more likely to be microamps or nanoamps, depending on the model. It's not possible, with a Y-axis scaled in milliamps, to clearly represent such a small area, and so this area is grossly exaggerated in the graph.
In this pedagogical context, I would argue that a collector current of 7mA is very far from cut-off, and the graph is misleading, but I understand why the exaggeration was necessary. In reality, you'll have a hard time finding a bipolar junction transistor whose collector current is millamps, when base current is zero.
So, if that graph isn't very helpful in the context of your question, we require a setup that does a better job, and can provide us with a graph showing clear transitions from one regime to another, while also showing the potentials of base, collector and emitter, to enable us to determine the biasing state of the two junctions:
simulate this circuit – Schematic created using CircuitLab
Take a look at base (blue) and collector (orange) potentials as I sweep V1:
The emitter is obviously held at 0V throughout.
In the region to the right of the right-most green marker, this is saturation. It is marked by the instant that collector potential falls below the base, causing the base-collector junction to become forward biased.
It is still possible for collector potential to continue to fall, approaching the emitter, but in practice it can only fall to within 0.1V or so of the emitter.
Your tutor is therefore correct to suggest that the state of saturation begins when both junctions are forward biased. Collector potential has fallen below the base, causing the B-C junction to be forward biased, even if only slightly, and the B-E junction is also still forward biased.
The state of cut-off is everything to the left of the left-most marker. Its precise position is debatable, since "cut-off" could be defined in different ways. Perhaps it means the state where collector current is insufficient to "operate" the load. Perhaps in some particular application it means the state where collector current is below 1% of saturation current. The definition of cut-off depends entirely on who you ask, and the context of the application.
However, in that graph, cut-off clearly ends somewhere in the region where collector potential begins to fall from its maximum of 3V. This is when collector current begins to rise from near-zero:
To the left, then, collector potential is always greater than the base, so in cut-off we can state correctly that the base-collector junction is reverse biased. However, the bias state of the base-emitter junction isn't so clearly defined. That can be reverse biased, or even slightly forward biased, without causing significant collector current. Cut-off ends when the base-emitter junction begins to conduct significant base current, which varies, but in general occurs somewhere near \$V_{BE} = 0.6V\$.
I think it's more accurate to say that both junctions reverse biased will create a cut-off state, but the B-E junction can even be slightly forward biased without leaving the cut-off state.
