The cutoff frequency of the amplifier is $$ \omega_c=\frac{1}{Req*C} $$ which when evaluated gives $$ \omega_c=\frac{1}{(6k\Omega ||4k\Omega)*10nF}=41666.66 rad/s$$
The answer is $$ 10^4 rad/s $$ This is true when taking RC in series with RL i.e.$$\omega_c=\frac{1}{(6k\Omega+4k\Omega)10nF}=10^4rad/s$$ 1. In AC analysis, shouldn't both the resistors (RC and RL) be in parallel?
2. We don't we consider the RB (input resistance) for cutoff frequency?
If you replace the transistor by its hybrid-\$\pi\$ model then you should see how the various resistances take place:
I am applying here the fast analytical circuits techniques or FACTs as described in my last book in the subject. You first need to determine the time constant of this circuit to obtain the pole value. You do it by calculating the resistance driving the capacitor when the input voltage - the stimulus - is zeroed. Zeroing a voltage source means replacing its symbol in the circuit by a short circuit. Redraw the sketch and inspect the circuit to determine the resistance "seen" from the capacitor's connecting terminals.
Once you have the time constant, you can reuse it with the high-frequency gain \$H^1\$ of the circuit obtained when the capacitor is replaced by a short circuit (\$s\$ approached infinity). Assemble these elements to form the transfer function:
I used an inverse pole notation to obtain a compact low-entropy transfer function that I can plot with Mathcad:
The ac response shows a zero at the origin and this is normal considering the capacitor acting as a dc-block device. The gain increases with a +1 slope until the pole breaks the slope to make it flat with a magnitude given by the \$H_{INF}\$ leading term in the transfer function.
1. In AC analysis, shouldn't both the resistors (RC and RL) be in parallel?
Answer: Yes, correct. This is because - as seen from the output of the current source (BJTs collector) - the ouput current Ic is split between Rc and RL. That means: For gain calculations both resistors are in parallel.
For the cut-off frequency we have to analyze the circuit from the capacitor side (and NOT from the collector side). Simplest method for finding the time constant of an RC combination: Find the current through the connected resistors - when the (charged) capacitor discharges. As we can see - the capacitor discharges through the resistors (left and right from the capacitor).
Thus, we must consider the series combination: Time constant T=C(RL+RC).
2. We don't we consider the RB (input resistance) for cutoff frequency?
Answer: When there is is no (external) coupling capacitance there is no input time constant and no corresponding lower cut-off frequency .
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Supplement: Time constant (high-pass cut-off) of the output RC combination shown circuit
From the circuit diagram it is evident (as mentioned already) that the time constant - as derived from the discharging process - is T=C(RC+RL). In particular, this is true because the BJT is treated as a (ideal) current source (no current into the collector during discharging of C).
Question: Will we arrive at the same result for the charging process? For this purpose, we have to generate the differential equation for the case that a current source I (input step) is charging the capacitor C.
Curent through RC is ic(t)=Vc/RC (Vc=collector voltage)
Current through C is io(t)=Vo/RL (Vo as shown in the drawing).
Current through C is the same: io(t)=C[d(Vc-Vo)/dt]
With Vc and Vo from the first two equations and with I=ic(t)+io(t) we arrive at the equation (dropping the brackets (t) for clarity):
io=C[(d(icRC - ioRL)/dt]=C[(d(I-io)RC - ioRL)/dt]
Beause d(I)/dt=0 we can write (after some minor manipulations)
io=-C(RC+RL)d(io)/dt.
Setting (Ansatz) io(t)=îo * exp(t/T) the solution of the diff. equation is
io(t)=îo * exp(t/T)=-C(RC+RL)(1/T) * îo * [exp(t/T)]
From this: T=-C(RC*RL)
Result (Summary): : The time constant T for the output circuitry can be calculated using (a) the discharging or (b) the charging process of the capacitor C.
Since this appears to be a basic electronics class, a simplification can be made which is the impedance of the collector of the transistor when in its linear mode is very high, i.e. the transistor is a nearly perfect current source. If you take the Thevenin equivalent of the collector circuit, you can come up with a first level approximation of the circuit. This is the type of mental simplification one can do when sussing out the characteristics of circuits.
simulate this circuit – Schematic created using CircuitLab
From this it should be clear that the cut off angular frequency is $$ w_c = {1 \over (Rc+RL)C1} $$
This will get you close, but if you want to really understand what's happening, you go into the detail Verbal Kint gives in his very educational answer.
