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Forgive me as my electrical knowledge is sub par, but if someone can help clear up what I am trying to understand that would be greatly appreciated.

Q8 is an N channel enhancement MOSFET. From my understanding, when Vgs == Vthresh of a NMOS, then the gate turns on.

The ON input is an output from an MCU which should be 3v3. The +12VHEAT line is an output from another chip that is enabled via the MCU as well. These two signals are enabled one after another when a specific instruction is made.

What I am trying to understand is how the MOSFET works here. If Vgs (ON) is == Vthresh then the gate should become active right? What if there's an issue with the MCU and +12V becomes active? Does that mean the output to the IC (which is a P channel MOSFET) is still active? What if just the ON line is active, and there is no 12V - does 3v3 just run to the IC? I guess I'm really trying to understand how the ON line influences this gate and how it goes to ground/why it does.

Here is the Circuit

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    \$\begingroup\$ Vgs(th) must be surpassed to ensure maximum power flow. Vgs(th) is when the MOSFET turns on, but not necessarily very well(poor conduction). Which FET are you referring to in your question, the IRF7226 or the NDS7002? \$\endgroup\$
    – lemon
    Commented Mar 1 at 8:08

2 Answers 2

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Below is the first stage, redrawn to have signals travel from left to right. I've drawn two identical instances of the same stage; on the left the input is 0V (digital low), and on the right the input is +3.3V (digital high):

schematic

simulate this circuit – Schematic created using CircuitLab

The potential difference \$V_{GS} = V_G - V_S\$ is what determines the conduction state of Q8's channel.

  • If \$V_{GS} >> V_{GS(TH)}\$ then the channel (between drain and source) is "on" and very conductive

  • If \$V_{GS} << V_{GS(TH)}\$ then that channel is "off", and conducts poorly.

Notice that the transistor's source is tied to ground, and so has a fixed potential of \$V_S=0V\$. This means that whatever potential \$V_G\$ applied to the gate will result in the following \$V_{GS}\$:

$$ V_{GS} = V_G - V_S = V_G - 0V = V_G $$

On the left, then, with \$V_{GS} = V_G = 0V\$, we expect the transistor's channel to be like an open switch, not conducting, allowing R95 and R96 to "pull up" the potential at X to \$V_X = +12V\$.

On the right, with \$V_{GS} = V_G = +3.3V\$, the transistor is on, like a closed switch, highly conductive, and the potential at X is "pulled down" to \$V_X = 0V\$.

If that's not clear enough, let me redraw those two scenarios with the transistors replaced by switches in those two states:

schematic

simulate this circuit

Notice that this stage both translates logic levels from +3.3V up to +12V, and inverts so that high in -> low out and vice versa.

The second stage is very similar to that, except it employs a P-channel MOSFET insead of N-channel, so the source is connected to +12V instead of ground (0V). Also, there is presumably a heating element, which I represent with RH here:

schematic

simulate this circuit

This time, we require the gate to be significantly lower in potential than the source, for the transistor to be switched on, since the transistor is P-channel. This means \$V_{GS}\$ must be strongly negative. Notice that the source is tied to +12V, so now \$V_{GS}\$ is calculated like this:

$$ V_{GS} = V_G - V_S = V_G - (+12V) $$

On the left, with \$V_G=+12V\$, we have:

$$ V_{GS} = (+12V) - (+12V) = 0V $$

Therefore we expect the transistor to be "off", highly resistive between drain and source. No current (well, nearly no current) flows due to this high resistance. With no current through it, heater RH has no potential difference across it, and it effectively "pulls down" the potential at OUT to 0V.

On the right, \$V_G = 0V\$:

$$ V_{GS} = (0V) - (+12V) = -12V $$

As stated above, this is the condition required for the transistor to be "on". The gate is significantly lower in potential than the source, so that \$V_{GS}\$ is strongly negative. That means the transistor conducts well. Node OUT is effectively connected directly to the +12V supply, and with the full 12V potential difference now across the heater RH, current flows restricted only by the heater's own resistance.

Again, these two scenarios can be represented with switches in the place of the transistors:

schematic

simulate this circuit

This stage also inverts. That is, high potential at X produces low potential at OUT and vice versa. In this case, a low input will switch on the heater.

Your original, complete circuit is simply the first and second stages cascaded one after the other. The way it's drawn is very difficult to follow, but everything's easier to understand when care is taken with schematic layout:

schematic

simulate this circuit

Hopefully it's clear now that:

  • 0V at IN causes +12V at X, which causes 0V at OUT, and no current flows in heater RH.

  • +3.3V at IN causes 0V at X, which causes +12V at OUT, and full current flows in heater RH.

A couple more notes:

  • R99 holds Q8's gate at 0V (avoiding a "floating" condition) in the absence of any explicit potential applied there. This ensures that the heater is off by default.

  • R96 is not necessary for this circuit to function. I suspect it is there to protect Q8 (and the microcontroller before it) from damage in the case that Q7 melts and becomes a source of unconstrained current direct from the power supply. R96 needs to be small compared to R95, since those two resistors form a potential divider, and we must avoid significantly altering (attenuating) the to 0V and +12V levels at X.


Additional note:

R95 is too large. Leakage current through Q8 can easily cause a significant voltage to develop across R95, which might partially switch on Q7. Just a few microamps of leakage current would cause this condition, and I recommend that R95 be 100kΩ instead. Leakage will depend on the model of Q8, which may well be specified to have sub-microamp leakage current (see "zero-gate-voltage drain current" in datasheets), but I think it's foolish to rely on such a parameter when it's so easy to mitigate.

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  • \$\begingroup\$ Thank you Simon! I really appreciate that in depth explanation. It's cleared up a lot, and I will have to study it more in depth to better my understanding of it. \$\endgroup\$
    – jabroni
    Commented Mar 4 at 6:09
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I'm going to take your circuit apart to make it easier to understand.

First, the P-channel MOSFET:

schematic

simulate this circuit – Schematic created using CircuitLab

This control the heater in your circuit. It switches the 12V power supply to the heater coil.

As long as the switch is open, the gate is at 12V, and no current flows. This type of P-channel MOSFET does not conduct when the gate is at the same voltage as the source. R1 holds the gate to the same voltage as the source as long as the switch is open. When the gate voltage is a few volts below the source voltage, the MOSFET conducts.

schematic

simulate this circuit

When the switch is closed, the gate is pulled to 0V and the P-channel MOSFET conducts. Current flows from the power supply through the MOSFET to the heater coil. The heater coil heats up.

Now we'll look at the N-channel MOSFET:

schematic

simulate this circuit

This type of N-channel MOSFET conducts when the gate is a few volts higher than the source. When the gate is at 0V and the source is at 0V, then no current flows.

schematic

simulate this circuit

When the "ON" signal is high (3.3V,) it causes the N-channel MOSFET to conduct. This pulls the gate of the P-channel MOSFET low which causes it to conduct and deliver current to the heater coil.

All together:

schematic

simulate this circuit

3.3V on the N-channel MOSFET gate turns on the heat.

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  • \$\begingroup\$ "This is the heater in your circuit. All it does is to short circuit the 12V power supply to ground." The drain of Q7 in the OP's diagram is not grounded. Q7 could also be just a switch to turn on a heater. It is a small SOIC after all. \$\endgroup\$
    – user319836
    Commented Mar 1 at 10:51
  • \$\begingroup\$ Hmm. Somehow I imagined a ground connection there. I'll fix it soon - I've got to go now. \$\endgroup\$
    – JRE
    Commented Mar 1 at 10:53
  • \$\begingroup\$ Thank you so much @JRE for the in depth explanation. It's cleared up a lot. \$\endgroup\$
    – jabroni
    Commented Mar 4 at 6:08

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