Below is the first stage, redrawn to have signals travel from left to right. I've drawn two identical instances of the same stage; on the left the input is 0V (digital low), and on the right the input is +3.3V (digital high):
simulate this circuit – Schematic created using CircuitLab
The potential difference \$V_{GS} = V_G - V_S\$ is what determines the conduction state of Q8's channel.
If \$V_{GS} >> V_{GS(TH)}\$ then the channel (between drain and source) is "on" and very conductive
If \$V_{GS} << V_{GS(TH)}\$ then that channel is "off", and conducts poorly.
Notice that the transistor's source is tied to ground, and so has a fixed potential of \$V_S=0V\$. This means that whatever potential \$V_G\$ applied to the gate will result in the following \$V_{GS}\$:
$$ V_{GS} = V_G - V_S = V_G - 0V = V_G $$
On the left, then, with \$V_{GS} = V_G = 0V\$, we expect the transistor's channel to be like an open switch, not conducting, allowing R95 and R96 to "pull up" the potential at X to \$V_X = +12V\$.
On the right, with \$V_{GS} = V_G = +3.3V\$, the transistor is on, like a closed switch, highly conductive, and the potential at X is "pulled down" to \$V_X = 0V\$.
If that's not clear enough, let me redraw those two scenarios with the transistors replaced by switches in those two states:
simulate this circuit
Notice that this stage both translates logic levels from +3.3V up to +12V, and inverts so that high in -> low out and vice versa.
The second stage is very similar to that, except it employs a P-channel MOSFET insead of N-channel, so the source is connected to +12V instead of ground (0V). Also, there is presumably a heating element, which I represent with RH here:
simulate this circuit
This time, we require the gate to be significantly lower in potential than the source, for the transistor to be switched on, since the transistor is P-channel. This means \$V_{GS}\$ must be strongly negative. Notice that the source is tied to +12V, so now \$V_{GS}\$ is calculated like this:
$$ V_{GS} = V_G - V_S = V_G - (+12V) $$
On the left, with \$V_G=+12V\$, we have:
$$ V_{GS} = (+12V) - (+12V) = 0V $$
Therefore we expect the transistor to be "off", highly resistive between drain and source. No current (well, nearly no current) flows due to this high resistance. With no current through it, heater RH has no potential difference across it, and it effectively "pulls down" the potential at OUT to 0V.
On the right, \$V_G = 0V\$:
$$ V_{GS} = (0V) - (+12V) = -12V $$
As stated above, this is the condition required for the transistor to be "on". The gate is significantly lower in potential than the source, so that \$V_{GS}\$ is strongly negative. That means the transistor conducts well. Node OUT is effectively connected directly to the +12V supply, and with the full 12V potential difference now across the heater RH, current flows restricted only by the heater's own resistance.
Again, these two scenarios can be represented with switches in the place of the transistors:
simulate this circuit
This stage also inverts. That is, high potential at X produces low potential at OUT and vice versa. In this case, a low input will switch on the heater.
Your original, complete circuit is simply the first and second stages cascaded one after the other. The way it's drawn is very difficult to follow, but everything's easier to understand when care is taken with schematic layout:
simulate this circuit
Hopefully it's clear now that:
0V at IN causes +12V at X, which causes 0V at OUT, and no current flows in heater RH.
+3.3V at IN causes 0V at X, which causes +12V at OUT, and full current flows in heater RH.
A couple more notes:
R99 holds Q8's gate at 0V (avoiding a "floating" condition) in the absence of any explicit potential applied there. This ensures that the heater is off by default.
R96 is not necessary for this circuit to function. I suspect it is there to protect Q8 (and the microcontroller before it) from damage in the case that Q7 melts and becomes a source of unconstrained current direct from the power supply. R96 needs to be small compared to R95, since those two resistors form a potential divider, and we must avoid significantly altering (attenuating) the to 0V and +12V levels at X.
Additional note:
R95 is too large. Leakage current through Q8 can easily cause a significant voltage to develop across R95, which might partially switch on Q7. Just a few microamps of leakage current would cause this condition, and I recommend that R95 be 100kΩ instead. Leakage will depend on the model of Q8, which may well be specified to have sub-microamp leakage current (see "zero-gate-voltage drain current" in datasheets), but I think it's foolish to rely on such a parameter when it's so easy to mitigate.