Changing the frequency or duty cycle won't change the ultimate long-term charge (voltage) across the output capacitor of the charge pump. I'll explain why here. I don't know what exact design you are using, but it will be some variation on this:
simulate this circuit – Schematic created using CircuitLab
The diodes behave like switches, opening and closing as the potential difference across them changes polarity. In practice they are not ideal, having some non-zero voltage across them (0.7V) when "closed", but to understand this circuit's behaviour, they can be envisaged as switches, either open or closed. Some designs (such as the implementation inside the famous ICL7660) employ transistors to exhibit more "ideal" behaviour (more closely mimicking actual switches), but the principle of operation remains the same.
During times when the CLK node is low (0V), D1 becomes forward biased, and conducts. This quickly charges C1 up to 5V:
simulate this circuit
When CLK rises to +5V, the lower terminal of C1 rises with it, taking node X above +5V in potential. D1 becomes reverse biased, no longer conducting, and D2 becomes forward biased, like a closed switch. This, then is the equivalent situation:
simulate this circuit
In this condition, with the potential of node X now above OUT, current \$I\$ flows, charging C2 beyond 5V also. OUT doesn't immediately rise to +10V, since current stops flowing when the two capacitors have the same charge (assuming C1 = C2). However, this process repeats, and C2 is charged a little during every cycle. Eventually C2's voltage approaches close enough to 10V to call it 10V. The result is a stepped rise of \$V_{OUT}\$, which is clear in a simulation:
To understand why changing the frequency or duty cycle of the CLK source has no (or little) effect on the long-term voltage across C2, it is necessary to see that the voltages across C1 and C2 change extremely rapidly. This is clearly visible in that graph; the vertical edges are just that - vertical, indicating that the charging and discharging of those two capacitors is instantaneous.
In real life those voltage transitions will not be instantaneous, of course, because the +5V source, and the CLK signal itself have some impedance which will slow the rise and fall of voltages across the capacitors, but the point here is that those transitions are very rapid. Once the system has settled following each CLK edge, nothing else happens. There are no changes occurring between those edges, everything happens immediately following the transitions of CLK.
These charging/discharging/transfer operations happen in microseconds, with nothing else going on for long durations (perhaps milliseconds) in between those transitions. Changing the frequency or duty cycle of CLK will only alter the duration between transitions, and will not significantly affect the amount of charge gained or transferred by the capacitors at each transition.
Ultimately, unless you can control how much charge is gained/transferred at each CLK transition, you have no control over the ultimate charge of C2, which means that PWM cannot help.
If you wish, you can produce a voltage lower than 10V at OUT by reducing the voltage that C1 charges to. For example, if you can somehow make CLK oscillate between +2V and +5V, then the difference (3V) will be added to C2's initial charge (+5V), for an eventual output of +8V:
