0
\$\begingroup\$

I am currently designing a MIPS single cycle CPU (32 bits) in Logisimenter image description here

I have already implemented the PC, instruction memory, register file and ALU. Since it is a 32 bits system I understand that the data bit width of every component should be 32 bits.

However when I tried to connect the output of my ALU to the data memory input (to implement the lw instruction) I realized the output of my ALU is 32bits meanwhile the maximum address bit width of my data memory is 24 bits.

The ALU is taking as inputs, register file input1, and a sign extended immediate, that is working as an offset for the actual memory address that need to be read.

How can I solve this problem?

\$\endgroup\$
1
  • \$\begingroup\$ Which MIPS? R2000? R3000? R4000? etc. Also, why no pipeline? Not that I can't come up with a single clock implementation. But why no pipeline (originally 5 stage for R2000, memory serving.) Also, it looks as though your instruction memory is using only 6 bits (A7 downto A2.) Intentional? Why don't you lay out your overall design details and show us the overall block diagram (with clocking inputs.) Your regfile should also have a write-data path. Not just 2 read-data paths. Write more to us? Also, your data memory address comes from the EX/MEM stage. What's the problem here?? I don't see it. \$\endgroup\$
    – periblepsis
    Commented Jun 13 at 7:41

1 Answer 1

Reset to default
0
\$\begingroup\$

You handle addressing data memory just the same as addressing instruction memory:

If your addresses are byte addresses and the memory is (4-byte) word addressed, don't connect A₀&A₁(A0&A1). Connect A₂ to the least significant memory address input, and from there up to however many address inputs your data memory has. (Conceptually - there used to be types of memory where every address input was equivalent and any permutation of address lines as good as any other. More often, there are two groups: row addresses and column addresses. Changing row address takes extra energy (and maybe time); so use the lower order address bits as column address input and permute for easiest routing (even in a schematic).)
Any remaining address signals go unused, too. (Logisim uses splitters(?))

\$\endgroup\$
4
  • \$\begingroup\$ The "design" looks a bit lacking. But the questioner does seem to have already stripped off A0 and A1 from the PC register (looking at the splitter there) and to only be using 6 bits (A7 downto A2) for addressing the instruction memory. I would expect the questioner to thus already know about the same idea with respect to data memory. I'm otherwise not all that hopeful. The diagram really looks ... like a lot is missing and no thoughts of pipelining... \$\endgroup\$
    – periblepsis
    Commented Jun 13 at 6:25
  • \$\begingroup\$ Yes, in Logisim you can use splitters to separate bus lines. \$\endgroup\$
    – the busybee
    Commented Jun 13 at 6:36
  • \$\begingroup\$ (@periblepsis would expect [Luigi_S_R already knows] the same idea [applies] to data memory The one explanation I find for asking above question is that this was missed.) \$\endgroup\$
    – greybeard
    Commented Jun 13 at 6:40
  • \$\begingroup\$ @greybeard Certainly worth dotting the i. Can't argue. ;) \$\endgroup\$
    – periblepsis
    Commented Jun 13 at 7:00

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.