The DNL of an ADC is defined as the measured code width versus the ideal LSB code width.
The INL is the integral of the DNL (or the running sum of it).
But the INL has two methods - end point and best fit. How is it possible there are two methods for INL calculation when it's simply the running sum of the DNL?
What changes in the INL calculation between end point and best fit methods?
INL is in general integral of error, not only DNL. It is true that DNL increases INL, but it isn't the only cause of INL.
Think of it this way, DNL is a discrete error, so error of converting analogue signal to digital, that is "making the steps". This is non linear by default, because you make steps from "linear" function of input voltagees. If the ADC would have no other non-linearity, DNL would absolutely also be INL (integrated). If i try to explain, steps would "roll" around linear line on input voltage vs code plot.
However, sadly there are other effects that curve that line previously linear response. If you were to send no. of bits to infinity the DNL would become zero or very small, but INL would still remain. By the way, i suggest looking into INL with frontend id ADC, Because INL in practice (INL of the system) is also dependent on input electronics. To explain what is different in calculating INL with both methods, you can imagine the following: In order to get rid of INL or diminish its effect, calibration is often used. Very simple method is just reading the end point and use the linear approximation from 0 to end point.
The other option is "best fit" (still linear). Basically the you use different reference of theoretical linear response for each case. While the INL can be higher for best fit, it can be (should be) much better fit around 1/2 of the input range, where ADCS are usually used the most. It can mean of course that the error will be greater at the full scale and zero scale. On the contrary, the end fit will give great results at zero and full scale, but will not be as good at half range.
Maybe it's easier to explain with awfully bad drawn plots representing performance of the worst ADC the world has ever seen :) :
On the top you can see and adc that has DNL (like they all do), but very little other non-linearity. On the bottom you can see ADC that has waaaay less DNL, but contribution of INL is still there. Even if there would be infinite bits, there would still be non-linearity. Red line shows theoretical response with regards to end point, while purple with best fit.
This example us very extreame, but just to give an idea.
I hope it helps :)
