Symmetric square wave duty cycle reduces with increase in frequency in push pull stage

Question

Source : https://www.allaboutcircuits.com/industry-articles/an-overview-of-driver-circuits-for-piezo-transducer-buzzers/

The transistors are MJE340 and MJE350 and NPN and PNP pair. I am using these since I need to be able to switch a good 100- 120.

I intend this stage to feed a LC filter to make the whole thing a class D amplifier, I want to pass a 33kHz PWM that will be demodulated through the filter.

to start with I send 50% duty cycle square wave through the input, I've noticed the following while reading the voltage at the emitter end.

1. The 'ON' time reduces with increased frequency, gradually reducing and turning close to a pulse/impulse around 15kHz and then disappearing altogether.

2. The greater the collector resistor on the first stage, the worse the above effect gets even at even lower frequencies.

3. Removing DC (Voltage was 0 to 5 volts DC) offset at the signal (voltage -2.5 to + 2.5) seems to fix the problem and I can see 50% duty cycle square wave all the way till 55kHz. This works but I'm not sure how to accomplish this, not sure a coupling capacitor at the base would do the trick since I don't quite see a way for it to discharge through the PN junction at the base.

What would best explain this behavior and what can I do about this?

Using this as a haptic actuator, it's a PowerHap 1919 and the source voltage goes all the way up to 120 volts max. I intend this as a class D amplifier, I have an LC low pass filter that works well enough with the actuator. If only I could get a 100 volt PWM signal into that, all would be good.

Answer 1

The duty cycle changing is explained by the asymmetric first stage. It just is not visible at low frequencies.

You have strong fast transistor that pulls signal down hard and fast with large sinking current. But only a resistor for sourcing current.

It means that the first stage can pull low fast but pushing high is slow.

It may be worsened by the fact how the first stage is driven, but assuming it is a logic level square wave from MCU or signal generator, the base drive turns the first stage transistor on hard, but it takes time to turn it off through the same resistor.

You can improve the driving of first stage by adding a diode which speeds up turning off the first stage.

In general, you might want to replace the whole thing with a level-shifting FET driver, a single IC that's capable of driving the second stage or even the speaker directly.

Edit: There's two ways of connecting a speedup diode - one is to put in in parallel to speed up discharge of current out of base even though it still saturates hard, but the other more effective way is a Baker Clamp between base and collector to prevent the transistor from saturating hard to begin with.

Also like I mentioned, whatever is after the first stage, you can see that the first stage transistor is strong and fast, it can discharge any charges in the load fast, sort of like think replacing it with a zero-ohm pushbutton. But when you release the pushbutton, whatever there is on the output, the drive and charging current is limited to slow speed by the resitor to positive voltage. Turn-on will be much slower than turn-off because turn on happens via some arbitrarily high resistance and turn-off happens via some arbitrarily low resistance.

So the first stage causes already duty cycle problems because both how it's input is driven and how it's output drives the next stage lengthens the low output.

Answer 2

You cannot design anything without an accurate model of the load. In this case, the load of the 1919 Haptic Piezo device is 2.5μF with an SRF (resonance) of 15 kHz so 20 kHz is beyond spec. and 10kHz may be a practical limit for thermal reasons depending on the power applied.

To see the impedance curve for 2.5 uF vs f follow the curve and your switch must be at most 5% of the impedance of the load for efficiency. It is easier just to use a 10A half-bridge CMOS switch if you plan on pushing the limits.

My suggested circuit design uses a sine or square drive, polar or bipolar with small adjustments to bias 12Vpp. Negative feedback gives better duty cycle symmetry with correct DC bias and more BW with lower gain. R.base will change with input drive level.

I assumed a 100Vdc supply and 2.2uF low ESR Piezo load with a Darlington NPN and I assumed hFE = 10 for the input NPN for Ic/Ib=10.

Conclusion

The OP's design goals need to no exceed the device specs.

Maximum operation frequency The operation frequency is limited by the self-heating of the component, which should not exceed +30 °C. This is reached after about 10 s of continuous square signal 0 ... 120 V at 500 Hz Maximum voltage change rate 1.2 MV/s

Answer 3

Try this circuit. It can easily drive close to 100mA into the load with only small duty cycle degradation at shown pulse drive frequency of around 100kHz.