In computer programming, it's easy to write code that operates sequentially, but in a logic circuit, where everything is on all at once, this isn't so simple.
Say I wanted to write some data to a register. I can't just set the data pins to their desired values and turn on the write-enable pin all at once, because this could lead to incorrect data being written as the data pins are transitioning at the same time as the write-enable pin. I'd have to turn on the write-enable pin after the data pins have finished transitioning and then turn it off before they transition to undefined values (or desired values for a different write).
How are modern high-speed logic circuits, for example in microprocessors, designed, on a logic gate level, to operate sequentially? Some possible ways I can think of are:
Perform only 1 operation per clock cycle. This means that it could take 3 clock cycles to write data to the aforementioned register. This may be acceptable if the microprocessor is able to run many other (independent) operations in parallel.
Have multiple clocks. Assuming your rise/fall times are fast, and your delay times are accurate, you could possibly generate multiple sub-clocks that operate at the same frequency as the main clock, but with different duty cycles and phase shifts.
Take propagation delay into account. Modern integrated circuit design software that generate both the logic circuit and die layout from hardware description languages could possibly take the speed of electricity through on-chip wires into account in order to emulate sub-clocks. In theory, this would be ideal, because it could create a microprocessor that operates near the absolute maximum performance.
Advanced logic algorithms. Perhaps there exists a way of transforming a sequential logic algorithm into a parallel logic algorithm.
