Verilog - variable number of inputs/outputs

Question

Is there a way in verilog to do the following? I have a variable number of FIFOs (1 to 4) created with a generate statement inside of a module

pseudocode:

module()
    generate( for i to NUM_FIFOS )
        FIFO fifoI( args )

What I want to do is have the read data from these FIFOs as outputs of the entire module. Is there a way to have a variable number of output?

e.g.

module(
    generate for( i = 0 to NUM_FIFOS )
        output FIFO_dataI
    )

Thanks for the help!

Answer 1

Use a parametrized bus width:

module FIFO #(WIDTH=8) (
  output [WIDTH-1:0] out,
   /* other ports */
);

Then overwrite the parameter when generating the instances.

module top #(NUM_FIFO=4,WIDTH_FIFO=8)(
  output [NUM_FIFO*WITDH_FIFO-1:0] FIFO_data,
   /* other ports */);
/* ... other code ... */
genvar i;
generate
    for(i=0; i<NUM_FIFO; i++) begin : gen_fifo
        FIFO #(.WIDTH(WIDTH_FIFO)) fifoI (
          .out( FIFO_data[i*WIDTH_FIFO +: WIDTH_FIFO] ),
          /* args */ );
    end : gen_fifo
endgenerate
endmodule : top