Concurrent assignment or output port connection should be a net type

Question

For the following code,I get several errors:

1)Target <mem> of concurrent assignment or output port connection should be a net type.

2)in_d0_ is not a constant

How this issue can be solved?

module module_cell44( in_d0,in_d1,in_d2,in_d3,out_61,out_68,clk );
    parameter DATA_WIDTH = 16;
    parameter ADDR_WIDTH = 8;
    parameter ADDR_DEPTH = 1 << ADDR_WIDTH;

// Interfaces
input clk;

input [DATA_WIDTH - 1:0] in_d0,in_d1,in_d2,in_d3;
output [DATA_WIDTH - 1:0] out_61,out_68;
reg [DATA_WIDTH - 1:0] out_61,in_d0_,in_d1_;
//Cell`s memory array
reg [DATA_WIDTH - 1:0] mem[0:ADDR_DEPTH - 1];


// Procedural Assignments

always @ ( posedge clk )
begin
in_d0_ <= in_d0;
in_d1_ <= in_d1;
mem[in_d2]<=in_d3;
end


// Continues Assinmnents

 assign mem[in_d0_] = in_d1_;

endmodule

Answer 1

You cannot drive a reg type via a continuous assignment (only a wire may be driven in this way).

If this is just modelling combinatorial logic, you could use a combinatorial always block:

always @* begin
    mem[in_d0_] = in_d1_;
end

However, this doesn't seem to make much sense to me for writing to a memory module, which is usually something that is written on a clock edge. Perhaps you want to make this a clocked block:

always @(posedge clk)
    mem[in_d0_] = in_d1_;
end

Answer 2

Although it is Cliff's proposal to remove Type Reg, as part of that, he explains Verilog types in detail in this paper.

This paper will detail the differences between register and net data types and propose an enhancement to the Verilog language that would eliminate the need to declare register data types altogether

A Proposal To Remove Those Ugly Register Data Types From Verilog